Abstract: An electrolyte for a lithium secondary battery and a lithium secondary battery including the same are disclosed herein. In some embodiments, an electrolyte for a lithium secondary battery includes a lithium salt, a non-aqueous solvent containing a fluorine-based organic solvent, and a fluorine-based compound represented by Formula 1. In some embodiments, a lithium secondary battery includes a positive electrode, a negative electrode, a separator disposed therebetween, and the electrolyte.

Abstract: Disclosed herein relates to an electrolyte composition and a lithium secondary battery including the same, wherein the electrolyte composition can not only effectively reduce gas generated during charging and discharging of the lithium secondary battery by including one or more electrolyte additives of a chemical compound represented by Formula 1 or a chemical compound represented by Formula 2, but also has the advantage of strengthening the SEI layer on the electrode surface, thereby improving the storage characteristics and life characteristics at high temperatures.

Abstract: An electrolyte composition with improved high temperature safety and a lithium secondary battery including the same is described herein. The electrolyte composition containing a primary additive comprising a compound represented by Formula 1, and specific amount of a secondary additive that contains one or more of cyclic carbonates, can not only reduce the generation of gas during secondary battery charge-discharge, but also improve storage characteristics and the lifespan characteristics under a high temperature condition by strengthening the SEI coating film on the surface of an electrode. wherein all the variables are described herein.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate including an active region defined by a device isolation layer, a bit line which is disposed on the substrate and extends in a first direction, a bit line contact which is disposed between the bit line and the substrate and connects the bit line to the active region, a bit line spacer which extends along a sidewall of the bit line, and a bit line contact spacer which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line.

Abstract: A semiconductor memory device may include a substrate including a cell region and a peripheral region along a periphery of the cell region; a cell region isolation layer along the periphery of the cell region in the substrate and defining the cell region; a cell conductive line on the cell region and including a sidewall on the cell region isolation layer; a peripheral gate conductive layer on the peripheral region and including a sidewall on the cell region isolation layer; and an isolation insulating layer in contact with the sidewall of the cell conductive line and the sidewall of the peripheral gate conductive layer on the cell region isolation layer.

Abstract: Provided is a piezoelectric property measuring apparatus for a liquid or viscous material. The piezoelectric property measuring apparatus includes a fixing jig having an inner space and an opened space; an operating jig configured to close the opened region of the inner space; a first electrode and a second electrode; a driving module moving the operating jig according to a driving signal; a motion information measuring module measuring motion information of the operating jig; a charge amount measuring module measuring the charge amount through the first electrode and the second electrode; and a control module generating the driving signal for the driving module, supplying the driving signal to the driving module, receiving the motion information, receiving charge amount information of the closed space, and measuring a piezoelectric property of the sample by using the motion information and the charge amount information.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: Provided is a piezoelectric property measuring apparatus for a liquid or viscous material. The piezoelectric property measuring apparatus includes a fixing jig having an inner space and an opened space; an operating jig configured to close the opened region of the inner space; a first electrode and a second electrode; a driving module moving the operating jig according to a driving signal; a motion information measuring module measuring motion information of the operating jig; a charge amount measuring module measuring the charge amount through the first electrode and the second electrode; and a control module generating the driving signal for the driving module, supplying the driving signal to the driving module, receiving the motion information, receiving charge amount information of the closed space, and measuring a piezoelectric property of the sample by using the motion information and the charge amount information.

Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: Provided are semiconductor devices including device isolation layers. The semiconductor device includes a substrate having a cell region and a core/peripheral region, a first active region in the cell region of the substrate, a first device isolation layer that defines the first active region, a second active region in the core/peripheral region of the substrate; and a second device isolation layer that defines the second active region. A height from a lower surface of the substrate to an upper end of the first device isolation layer in a first direction that is perpendicular to the lower surface of the substrate is less than or equal to a height from the lower surface of the substrate to an upper end of the first active region in the first direction.

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Abstract: The present disclosure relates to a cosmetic composition having piezoelectricity. More particularly, the present disclosure relates to a piezoelectric cosmetic composition which includes a piezoelectric material capable of generating microcurrent upon the application of pressure as an active ingredient. According to the present disclosure, when the piezoelectric composition is applied to and massaged on the skin, it is possible to maximize an effect of skin care, including an effect of improving skin elasticity, by generating microcurrent.

Abstract: A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.