Abstract: An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the substrate, a first P? region in an anode region of the n-type epitaxial layer, a first N+ region in the first P? region, an N-well in a cathode region of the n-type epitaxial layer, a first P+ region in the N-well, and a second N+ region located in the N-well. The first N+ region may be located closer to the second N+ region than the first P+ region.

Abstract: An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the substrate, a first P? region in an anode region of the n-type epitaxial layer, a first N+ region in the first P? region, an N-well in a cathode region of the n-type epitaxial layer, a first P+ region in the N-well, and a second N+ region located in the N-well. The first N+ region may be located closer to the second N+ region than the first P+ region.

Abstract: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.

Abstract: Stacked SCR's are disclosed with a resistor connecting an internal portion of the upper SCR to an internal portion of the lower SCR. The anode of the protective circuit is connected to a contact on a target circuit to be protected and the cathode of the protective circuit is connected to ground or a reference voltage on the target circuit. The anode voltage is directed to the lower SCR via the resistor such that when the voltage on the anode reaches the triggering voltage of the lower SCR, that SCR triggers and that triggering triggers the upper SCR, such that the stacked SCR's both trigger and thereby limit the voltage between the anode and the cathode and thereby protecting the target circuit.

Abstract: Stacked SCR's are disclosed with a resistor connecting an internal portion of the upper SCR to an internal portion of the lower SCR. The anode of the protective circuit is connected to a contact on a target circuit to be protected and the cathode of the protective circuit is connected to ground or a reference voltage on the target circuit. The anode voltage is directed to the lower SCR via the resistor such that when the voltage on the anode reaches the triggering voltage of the lower SCR, that SCR triggers and that triggering triggers the upper SCR, such that the stacked SCR's both trigger and thereby limit the voltage between the anode and the cathode and thereby protecting the target circuit.

Abstract: A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few volts above ground, but when Vcc is high the trigger point of the SCR protecting the I/O node is much higher. The dual SCR incorporates added diffusions to an existing first SCR structure between the power node and the ground node thereby forming a second SCR. The first and second SCRs share a common cathode transistor. In one illustrative embodiment, only one SCR is constructed incorporating the Vcc to control the triggering of the SCR.