Patents by Inventor Jun-Hyeub Sun
Jun-Hyeub Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9437444Abstract: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer.Type: GrantFiled: October 24, 2013Date of Patent: September 6, 2016Assignee: SK HYNIX INC.Inventors: Sung-Kwon Lee, Jun-Hyeub Sun, Ho-Jin Jung, Chun-Hee Lee
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Patent number: 9425072Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.Type: GrantFiled: July 17, 2014Date of Patent: August 23, 2016Assignee: SK Hynix Inc.Inventors: Jun-Hyeub Sun, Sung-Kwon Lee, Sang-Oh Lee
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Publication number: 20140326408Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Jun-Hyeub SUN, Sung-Kwon LEE, Sang-Oh LEE
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Publication number: 20140322915Abstract: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer.Type: ApplicationFiled: October 24, 2013Publication date: October 30, 2014Applicant: SK hynix Inc.Inventors: Sung-Kwon LEE, Jun-Hyeub SUN, Ho-Jin JUNG, Chun-Hee LEE
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Patent number: 8846540Abstract: A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.Type: GrantFiled: December 12, 2012Date of Patent: September 30, 2014Assignee: SK Hynix Inc.Inventors: Sung-Kwon Lee, Jun-Hyeub Sun, Young-Kyun Jung
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Patent number: 8841195Abstract: A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure.Type: GrantFiled: September 7, 2012Date of Patent: September 23, 2014Assignee: SK Hynix Inc.Inventors: Jun-Hyeub Sun, Sang-Oh Lee, Su-Young Kim
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Patent number: 8785328Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.Type: GrantFiled: September 10, 2012Date of Patent: July 22, 2014Assignee: SK Hynix Inc.Inventors: Jun-Hyeub Sun, Sung-Kwon Lee, Sang-Oh Lee
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Publication number: 20140162453Abstract: A semiconductor device that may prevent an unexposed substrate and generation of bowing profile during a process for forming an open region having a high aspect ratio, and a method for fabricating the semiconductor device. The semiconductor device includes a first material layer formed over a substrate, an open region formed in the first material layer that exposes the first material layer, a second material layer formed on sidewalls of the open region, wherein the second material layer is a compound material including an element of the first material layer, and a conductive layer formed inside the open region.Type: ApplicationFiled: February 14, 2014Publication date: June 12, 2014Applicant: SK hynix Inc.Inventors: Sung-Kwon LEE, Jun-Hyeub SUN, Su-Young KIM, Jong-Sik BANG
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Publication number: 20140057442Abstract: A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.Type: ApplicationFiled: December 12, 2012Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: Sung-Kwon LEE, Jun-Hyeub SUN, Young-Kyun JUNG
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Publication number: 20130337652Abstract: A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.Type: ApplicationFiled: September 10, 2012Publication date: December 19, 2013Inventors: Jun-Hyeub SUN, Sung-Kwon Lee, Sang-Oh Lee
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Publication number: 20130328196Abstract: A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure.Type: ApplicationFiled: September 7, 2012Publication date: December 12, 2013Inventors: Jun-Hyeub Sun, Sang-Oh Lee, Su-Young Kim
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Publication number: 20130037961Abstract: A semiconductor device that may prevent an unexposed substrate and generation of bowing profile during a process for forming an open region having a high aspect ratio, and a method for fabricating the semiconductor device. The semiconductor device includes a first material layer formed over a substrate, an open region formed in the first material layer that exposes the first material layer, a second material layer formed on sidewalls of the open region, wherein the second material layer is a compound material including an element of the first material layer, and a conductive layer formed inside the open region.Type: ApplicationFiled: December 21, 2011Publication date: February 14, 2013Inventors: Sung-Kwon LEE, Jun-Hyeub SUN, Su-Young KIM, Jong-Sik BANG
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Patent number: 8308966Abstract: A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.Type: GrantFiled: June 30, 2009Date of Patent: November 13, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang, Sang-Min Ju
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Patent number: 8222152Abstract: A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.Type: GrantFiled: May 5, 2010Date of Patent: July 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jun-Hyeub Sun
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Publication number: 20120009523Abstract: A method for forming a contact hole of a semiconductor device, includes forming a hard mask over an etch target layer, forming a first line pattern over the hard mask, forming a second line pattern over the hard mask and the first line pattern in a direction crossing the first line pattern, forming a mesh-type hard mask pattern by etching the hard mask using the first and second line patterns as etch barriers, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.Type: ApplicationFiled: October 1, 2010Publication date: January 12, 2012Inventors: Sung-Kwon LEE, Cheol-Kyu Bok, Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang
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Patent number: 8012881Abstract: A method for forming contact holes in a semiconductor device includes forming a hard mask layer over an etch target layer, forming a first line pattern in the hard mask layer by etching a portion of the hard mask layer through a primary etch process, forming a second line pattern crossing the first line pattern by etching the hard mask layer including the first line pattern through a secondary etch process, and etching the etch target layer by using the hard mask layer including the first line pattern and the second line pattern as an etch barrier.Type: GrantFiled: August 11, 2010Date of Patent: September 6, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Oh Lee, Sung-Kwon Lee, Jun-Hyeub Sun, Jong-Sik Bang
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Publication number: 20110159693Abstract: A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.Type: ApplicationFiled: May 5, 2010Publication date: June 30, 2011Inventor: Jun-Hyeub SUN
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Patent number: 7919414Abstract: A method for forming fine patterns in a semiconductor device includes forming an etch stop layer and a sacrificial layer over an etch target layer, forming photoresist patterns over the sacrificial layer, etching the sacrificial layer by using the photoresist patterns as an etch barrier to form sacrificial patterns, forming spacers on both sidewalls of the sacrificial patterns, removing the sacrificial patterns, and etching the etch stop layer and the etch target layer by using the spacer as an etch barrier.Type: GrantFiled: December 26, 2007Date of Patent: April 5, 2011Assignee: Hynix Semiconductor Inc.Inventors: Won-Kyu Kim, Jun-Hyeub Sun
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Publication number: 20100248491Abstract: A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.Type: ApplicationFiled: June 30, 2009Publication date: September 30, 2010Inventors: Jun-Hyeub Sun, Shi-Young Lee, Jong-Sik Bang, Sang-Min Ju
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Patent number: 7790546Abstract: A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.Type: GrantFiled: July 7, 2008Date of Patent: September 7, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jun-Hyeub Sun, Sung-Kwon Lee, Sung-Yoon Cho