Patents by Inventor Jun-Hyoung Kim
Jun-Hyoung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088045Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Jun Hyoung KIM, Young-Jin KWON, Geun Won LIM
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Patent number: 11862566Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.Type: GrantFiled: September 11, 2020Date of Patent: January 2, 2024Inventors: Jun Hyoung Kim, Young-Jin Kwon, Geun Won Lim
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Publication number: 20230303180Abstract: An embodiment vehicle rear structure includes a rear pillar, including a rear pillar inner and a plurality of reinforcements mounted on the rear pillar inner. A component mounting bracket is attached to the rear pillar and has a receiving portion in which a portion of a vehicle component is received. The reinforcements are disposed to surround the component mounting bracket.Type: ApplicationFiled: August 26, 2022Publication date: September 28, 2023Inventors: Young Eun Kim, Jun Hyoung Kim, Seong Hoon Ham
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Publication number: 20230222891Abstract: A method for monitoring a dangerous situation in a space based on a frequency response pattern according to an embodiment includes loading, by a processing unit of a mobile terminal located in the arbitrary space, a setting value corresponding to an operational mode selected through control software installed on the mobile terminal, controlling, by the processing unit, a speaker of the mobile terminal to generate a frequency corresponding to the loaded setting value, receiving the frequency which was generated in the controlling and reflected in the space through a microphone of the mobile terminal, determining, by the processing unit, whether the dangerous situation occurred in the space by comparing the frequency response pattern with a preset reference value, and taking, by the processing unit, a follow-up action when it is determined that the dangerous situation occurred in the space by the determining.Type: ApplicationFiled: November 29, 2022Publication date: July 13, 2023Inventors: Seung-Yub KOO, Seong-Taek HWANG, Sung-Eon KONG, Jun-Hyoung KIM
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Patent number: 11613845Abstract: The present invention relates to an apparatus for manufacturing artificial leather, the apparatus including an embossing molding device capable of efficiently forming an embossed pattern on the surface of artificial leather through vacuum adsorption molding and a method of manufacturing artificial leather using the apparatus.Type: GrantFiled: September 11, 2018Date of Patent: March 28, 2023Assignee: LG Hausys, Ltd.Inventors: Kitae Kim, Jun Hyoung Kim, Eun Sik Nam, Jae Bong Hwang
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Publication number: 20220130851Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Inventors: Jun Hyoung KIM, Kwang Soo KIM, Seok Cheon BAEK, Geun Won LIM
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Patent number: 11264401Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.Type: GrantFiled: February 7, 2019Date of Patent: March 1, 2022Inventors: Jun Hyoung Kim, Kwang Soo Kim, Seok Cheon Baek, Geun Won Lim
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Publication number: 20210210431Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.Type: ApplicationFiled: September 11, 2020Publication date: July 8, 2021Inventors: Jun Hyoung KIM, Young-Jin KWON, Geun Won LIM
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Patent number: 10991714Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.Type: GrantFiled: December 18, 2018Date of Patent: April 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Kim, Jun Hyoung Kim, Si Wan Kim, Kyoung Taek Oh
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Patent number: 10858047Abstract: Disclosed are a partition panel for vehicles and a method of manufacturing the same. The method includes mounting a first prepreg formed to have a shape corresponding to a molding groove on a lower die provided with the molding groove. The molding groove is inclined upwards from the center of a lower portion of the lower die to opposite ends of the lower die. A second prepreg having a sheet type is mounted on the lower die so as to cover the first prepreg. The first prepreg and the second prepreg are integrally molded by placing an upper die on the lower die.Type: GrantFiled: January 15, 2019Date of Patent: December 8, 2020Assignees: Hyundai Motor Company, Kia Motors Corporation, Hanwha Solutions CorporationInventors: Min Soo Kim, Wook Hyun Han, Chang Dong Kim, Jun Hyoung Kim, Jun Young Kim, Sang Sun Park, Joung Myung Lim, Ji Hwan Choi, Hee Young Ko
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Patent number: 10861877Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.Type: GrantFiled: July 13, 2020Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jun Hyoung Kim
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Publication number: 20200354888Abstract: The present invention relates to an apparatus for manufacturing artificial leather, the apparatus including an embossing molding device capable of efficiently forming an embossed pattern on the surface of artificial leather through vacuum adsorption molding and a method of manufacturing artificial leather using the apparatus.Type: ApplicationFiled: September 11, 2018Publication date: November 12, 2020Inventors: Kitae KIM, Jun Hyoung KIM, Eun Sik NAM, Jae Bong HWANG
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Publication number: 20200350331Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.Type: ApplicationFiled: July 13, 2020Publication date: November 5, 2020Inventor: Jun Hyoung Kim
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Patent number: 10797071Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.Type: GrantFiled: January 18, 2019Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Hyoung Kim, Kwang Soo Kim, Geun Won Lim
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Patent number: 10748924Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.Type: GrantFiled: December 28, 2018Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jun Hyoung Kim
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Patent number: 10685980Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.Type: GrantFiled: February 6, 2019Date of Patent: June 16, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Kim, Si Wan Kim, Jun Hyoung Kim, Kyoung Taek Oh, Bong Hyun Choi
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Publication number: 20200058671Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.Type: ApplicationFiled: February 7, 2019Publication date: February 20, 2020Inventors: Jun Hyoung KIM, Kwang Soo KIM, Seok Cheon BAEK, Geun Won LIM
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Publication number: 20200020716Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.Type: ApplicationFiled: January 18, 2019Publication date: January 16, 2020Inventors: Jun Hyoung KIM, Kwang Soo KIM, Geun Won LIM
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Publication number: 20190393240Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.Type: ApplicationFiled: February 6, 2019Publication date: December 26, 2019Inventors: Kwang Soo KIM, Si Wan Kim, Jun Hyoung Kim, Kyoung Taek Oh, Bong Hyun Choi
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Publication number: 20190378855Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.Type: ApplicationFiled: December 18, 2018Publication date: December 12, 2019Inventors: Kwang Soo KIM, Jun Hyoung KIM, Si Wan KIM, Kyoung Taek OH