Abstract: A memory system includes a memory device having a plurality of memory blocks and a subcommand storage circuit, and a memory controller for controlling the memory device, wherein the memory device is capable of being in one or more of a ready state, a first busy state, and a second busy state, and wherein the subcommand is stored in the subcommand storage circuit when the subcommand is received from the memory controller in the first busy state and the subcommand is executable after the first busy state is released, and the subcommand stored in the subcommand storage circuit is executed after the memory device is changed to the ready state.

Abstract: A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.

Abstract: Provided is a method for manufacturing reduced iron which includes the steps of: i) drying ores in an ore drier; ii) supplying the dried ores to at least one reduction reactor; iii) reducing the ores in the at least one reduction reactor and manufacturing reduced iron; iv) discharging exhaust gas by which the ores are reduced in the reduction reactor; v) branching the exhaust gas and providing the branched exhaust gas as ore feeding gas; and vi) exchanging heat between the exhaust gas and the ore feeding gas and transferring the sensible heat of the exhaust gas to the ore feeding gas. In the supplying the dried ores to the at least one reduction reactor, the dried ores are supplied to the at least one reduction reactor by using the ore feeding gas.

Abstract: Provided is a method for manufacturing reduced iron which includes the steps of: i) drying ores in an ore drier; ii) supplying the dried ores to at least one reduction reactor; iii) reducing the ores in the at least one reduction reactor and manufacturing reduced iron; iv) discharging exhaust gas by which the ores are reduced in the reduction reactor; v) branching the exhaust gas and providing the branched exhaust gas as ore feeding gas; and vi) exchanging heat between the exhaust gas and the ore feeding gas and transferring the sensible heat of the exhaust gas to the ore feeding gas. In the supplying the dried ores to the at least one reduction reactor, the dried ores are supplied to the at least one reduction reactor by using the ore feeding gas.

Abstract: Provided is an apparatus for manufacturing reduced iron and a method for manufacturing reduced iron. The method for manufacturing reduced iron includes the steps of: i) drying ores in an ore drier; ii) supplying the dried ores to at least one reduction reactor; iii) reducing the ores in the at least one reduction reactor and manufacturing reduced iron; iv) discharging exhaust gas by which the ores are reduced in the reduction reactor; v) branching the exhaust gas and providing the branched exhaust gas as ore feeding gas; and vi) exchanging heat between the exhaust gas and the ore feeding gas and transferring the sensible heat of the exhaust gas to the ore feeding gas. In the steps of supplying the dried ores to the at least one reduction reactor, the dried ores are supplied to the at least one reduction reactor by using the ore feeding gas.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.

Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.

Abstract: A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.

Abstract: A method and apparatus for setting an alarm in a portable terminal are provided. The method includes receiving a message for requesting the setting of the alarm from a peer terminal, confirming a right of the peer terminal to set an alarm, determining, if the peer terminal has the right to set the alarm, an alarm generation time according to a transmission time of the alarm setting request message, and setting the alarm for the alarm generation time.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.

Abstract: A nonvolatile memory device includes a substrate including a plurality of active regions which are constituted by a P-type semiconductor; first and second vertical strings disposed over each active region, wherein each of the first and second strings includes a channel vertically extending from the substrate, a plurality of memory cells, and a select transistor, wherein the plurality of memory cells and the select transistor are located along the channel; and a bottom gate being interposed between a lowermost memory cell and the substrate, contacting the channel with a first gate dielectric layer interposed therebetween, and controlling connection of the first vertical string with the second vertical string.

Abstract: A distributor bottom, particularly a nozzle-type distributor bottom, for steadily introducing process gas, especially process gas loaded with solid particles, into a process chamber, optionally to create a fluidized bed. The process chamber is disposed above the distributor bottom and is formed by walls of a reactor used for metallurgically, particularly thermally, treating feedstock. The distributor bottom is provided with a plurality of holes. Holes are arranged near the walls to prevent substances from attaching to the reactor walls. Special arrangements relate to nozzles and ducts.