Patents by Inventor Junhyung Um

Junhyung Um has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8819310
    Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bub-chul Jeong, Jaegeun Yun, Junhyung Um, Jung-Sik Lee, Hyun-Joon Kang, Sung-Min Hong, Ling Ling Liao
  • Patent number: 8582709
    Abstract: Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegeun Yun, Hyunuk Jung, Junhyung Um, Sunghoon Shim, Sung-Min Hong, Bub-chul Jeong
  • Patent number: 8443122
    Abstract: An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JaeGeun Yun, Junhyung Um, Woo-Cheol Kwon, Hyun-Joon Kang, Bub-chul Jeong
  • Publication number: 20120131246
    Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.
    Type: Application
    Filed: October 19, 2011
    Publication date: May 24, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bub-chul Jeong, Jaegeun Yun, Junhyung Um, Jung-Sik Lee, Hyun-Joon Kang, Sung-Min Hong, Ling Ling Liao
  • Publication number: 20120089758
    Abstract: At least one example embodiment discloses a System on Chip (SoC). The SoC includes a master block, a plurality of slave blocks configured to operate in response to a request from the master block, and an interconnect block configured to deliver transactions occurring in the master block to the plurality of slave blocks through a plurality of transfer paths. The interconnect block is configured to monitor load information of the plurality of transfer paths and select one of the plurality of transfer paths according to the load information.
    Type: Application
    Filed: July 8, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaegeun Yun, Bub-chul Jeong, Junhyung Um, Hyun-Joon Kang, Sung-Min Hong, LIAOLINGLING
  • Publication number: 20110131350
    Abstract: An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.
    Type: Application
    Filed: November 2, 2010
    Publication date: June 2, 2011
    Inventors: JaeGeun Yun, Junhyung Um, WooCheol Kwon, Hyun-Joon Kang, Bub-chul Jeong
  • Publication number: 20110122982
    Abstract: Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.
    Type: Application
    Filed: October 1, 2010
    Publication date: May 26, 2011
    Inventors: Jaegeun Yun, Hyunuk Jung, Junhyung Um, Sunghoon Shim, Sung-Min Hong, Bub-chul Jeong