Patents by Inventor Junichi Shibata

Junichi Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413566
    Abstract: In one embodiment, a semiconductor device includes a first substrate, a first transistor provided on an upper face of the first substrate, and a memory cell array provided above the first transistor. The device further includes a second substrate provided above the memory cell array, and a second transistor provided on an upper face of the second substrate.
    Type: Application
    Filed: February 14, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Hideto TAKEKIDA, Junichi SHIBATA
  • Publication number: 20230282633
    Abstract: A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.
    Type: Application
    Filed: April 10, 2023
    Publication date: September 7, 2023
    Inventor: Junichi SHIBATA
  • Patent number: 11658169
    Abstract: A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventor: Junichi Shibata
  • Publication number: 20230075178
    Abstract: A molded article or an electrical product facilitates layout of a wiring line from an electrical circuit of a circuit film integrally molded with a molded body to a connection terminal. The molded article includes a circuit film and a molded body. The circuit film includes an insulating film and an electrical circuit. The molded body is integrally molded with the circuit film. The circuit film includes a flexible wiring portion. The molded body has a through-hole that penetrates from a first main surface to a second main surface. In the flexible wiring portion, a connection terminal is arranged at a position of passing through the through-hole and beyond the second main surface.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 9, 2023
    Applicant: NISSHA CO.,LTD.
    Inventors: Chuzo TANIGUCHI, Ryomei OMOTE, Eiji KAWASHIMA, Junichi SHIBATA, Jun SASAKI, Yoshihiro SAKATA
  • Patent number: 11534846
    Abstract: A wire electrical discharge machine to cut a workpiece by generating an electrical discharge in a dielectric working fluid between wire electrodes arranged in parallel and the workpiece includes: a work tank that stores the dielectric working fluid; a Z-axis stage that is disposed in a lower portion of the work tank and moves the workpiece in a Z-axis direction that is a vertical direction; a pillar that extends upward from the Z-axis stage and has an upper end portion located above the highest level of a fluid level of the dielectric working fluid in the work tank; an adjuster that is installed downward from a portion of the pillar located above the highest level of the fluid level, is disposed above the highest level of the fluid level, and adjusts the position or posture of the workpiece in a direction other than the vertical direction.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: December 27, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takashi Yuzawa, Yoichi Otomo, Junichi Shibata
  • Publication number: 20220302152
    Abstract: In one embodiment, a semiconductor device includes first electrode layers spaced from one another in a first direction, and second electrode layers provided above the first electrode layers, and spaced from one another in the first direction. The device further includes a first columnar portion extending in the first direction in the first electrode layers, and including a first semiconductor layer, and a second columnar portion provided on the first columnar portion, extending in the first direction in the second electrode layers, and including a second semiconductor layer. The first columnar portion includes a first portion having a first width, and a second portion having a second width larger than the first width above the first portion. The second columnar portion includes a third portion having a third width, and a fourth portion having a fourth width larger than the third width above the third portion.
    Type: Application
    Filed: September 14, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Koichi SAKATA, Junichi SHIBATA
  • Publication number: 20220252778
    Abstract: An illumination display panel that forms part of a housing and has a display portion for illuminated display comprises a resin panel having a first molded portion made of an opaque resin at a portion excluding the display portion, and a second molded portion disposed on the back surface side of the first molded portion and made of a light-transmitting resin having a protrusion where the first molded portion is not present. The protrusion is fitted to the first molded portion. A light source mounting substrate is disposed on the back surface side of the resin panel. At least a light source of the light source mounting substrate is sealed by the second molded portion. An integrally molded product of the light source mounting substrate and the second molded portion is filled and solidified at a low pressure while compressing a cavity of a molding mold.
    Type: Application
    Filed: August 17, 2020
    Publication date: August 11, 2022
    Inventors: Chuzo TANIGUCHI, Ryomei OMOTE, Junichi SHIBATA, Jun SASAKI, Yoshihiro SAKATA, Toshifumi KUROSAKI, Shohei MORIMOTO
  • Publication number: 20220143724
    Abstract: A wire electrical discharge machine to cut a workpiece by generating an electrical discharge in a dielectric working fluid between wire electrodes arranged in parallel and the workpiece includes: a work tank that stores the dielectric working fluid; a Z-axis stage that is disposed in a lower portion of the work tank and moves the workpiece in a Z-axis direction that is a vertical direction; a pillar that extends upward from the Z-axis stage and has an upper end portion located above the highest level of a fluid level of the dielectric working fluid in the work tank; an adjuster that is installed downward from a portion of the pillar located above the highest level of the fluid level, is disposed above the highest level of the fluid level, and adjusts the position or posture of the workpiece in a direction other than the vertical direction.
    Type: Application
    Filed: April 5, 2019
    Publication date: May 12, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi YUZAWA, Yoichi OTOMO, Junichi SHIBATA
  • Publication number: 20220059481
    Abstract: A semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate, transistors, a first interconnect, and first bonding electrodes. The second chip includes a memory cell array and second bonding electrodes. The second bonding electrodes are bonded to the first bonding electrodes. The first chip or the second chip has bonding pad electrodes. The second bonding electrodes include third bonding electrodes and fourth bonding electrodes. The third and fourth bonding electrodes overlap the memory cell array. The third bonding electrodes are in a current pathway between the memory cell array and the transistors whereas the fourth bonding electrodes are not in such a current pathway. The first interconnect is electrically connected to a bonding pad electrode and a fourth bonding electrode directly, without a current path via any one of transistors.
    Type: Application
    Filed: March 1, 2021
    Publication date: February 24, 2022
    Inventor: Junichi SHIBATA
  • Publication number: 20210296299
    Abstract: A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Inventor: Junichi SHIBATA
  • Patent number: 10998287
    Abstract: In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Junichi Shibata
  • Publication number: 20200354273
    Abstract: Provided is a novel metallic coarse aggregate for concrete which can be used as a coarse aggregate which is one of the essential constituents of concrete, can further improve the compressive strength and tensile strength of concrete, is less likely to be sedimented in fresh concrete, and has good productivity at a low cost. The metallic coarse aggregate for concrete includes a coarse aggregate body including a spherical cap portion bonded body having two hollow spherical cap portions and an annular portion protruding from a surface of the spherical cap portion bonded body so as to surround an outer periphery of the spherical cap portion bonded body, the annular portion having a shape in which a corner of a rectangular shape is bent upward or downward.
    Type: Application
    Filed: March 30, 2020
    Publication date: November 12, 2020
    Applicant: IBH SHIBATA, INC.
    Inventors: Junichi SHIBATA, Manzo UCHIGASAKI
  • Publication number: 20200294958
    Abstract: In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Junichi SHIBATA
  • Publication number: 20200251490
    Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer.
    Type: Application
    Filed: July 26, 2019
    Publication date: August 6, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Sota MATSUMOTO, Junichi SHIBATA, Takahito NISHIMURA, Kazuhiro WASHIDA
  • Patent number: 10483124
    Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masakazu Sawano, Takahiro Tomimatsu, Junichi Shibata, Hideki Inokuma, Hisashi Kato, Kenta Yoshinaga
  • Publication number: 20190214268
    Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.
    Type: Application
    Filed: September 10, 2018
    Publication date: July 11, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masakazu SAWANO, Takahiro TOMIMATSU, Junichi SHIBATA, Hideki INOKUMA, Hisashi KATO, Kenta YOSHINAGA
  • Patent number: 9933877
    Abstract: Problem: To achieve a pressure sensitive sensor capable of suppressing a drop in the accuracy of detecting a pressing force even in cases where the ambient temperature changes. Resolution means: A pressure sensitive sensor (7) includes: an elastically deformable covering member (10A) covering a front surface side; a variable resistance electrode (42A), electrical resistance thereof changing in response to a change in posture; a pyroelectric material layer (50) disposed covering the variable resistance electrode (42A); and a pair of charge detection electrodes (51, 52) disposed on both sides of the pyroelectric material layer (50) in a layering direction (L).
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: April 3, 2018
    Assignee: Nissha Co., Ltd.
    Inventors: Yuji Watazu, Naoto Imae, Keisuke Ozaki, Eiji Kakutani, Junichi Shibata
  • Patent number: 9921705
    Abstract: A resistive film type touch panel includes a transparent insulating film, a plurality of upper electrodes, and a plurality of routing wires. The plurality of upper electrodes are formed on the lower surface of the transparent insulating film and are arranged in a direction, and includes a group of the electrodes electrically connected with each other. The electrical combinations of the detection electrodes adjacent with each other in the direction of a planned simultaneous detection number are different from one another. The plurality of routing wires extend from the plural upper electrodes, and are formed in a frame area outside of the plurality of upper electrodes on the lower surface. Thus, the number of the electrodes is increased in order to improve the resolution, while also miniaturizing the touch panel.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: March 20, 2018
    Assignee: Nissha Co., Ltd.
    Inventor: Junichi Shibata
  • Patent number: 9904430
    Abstract: An antenna-equipped touch panel is one that is laminated on a display device in order to be used. The antenna-equipped touch panel includes an antenna pattern including an antenna element and a first wire of an antenna, the first wire being electrically connected to the antenna element; and a detection pattern including electrodes and second wires of the touch panel, the second wires being electrically connected to the electrodes. In plan perspective view, a shortest distance between the antenna pattern and the detection pattern is greater than or equal to 1.0 mm and less than or equal to 20.0 mm.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 27, 2018
    Assignee: NISSHA CO., LTD.
    Inventors: Junichi Shibata, Inyeol Moon, Shuzo Okumura
  • Patent number: 9885620
    Abstract: In a pressure detecting apparatus, a pressure sensor includes a piezoelectric sheet that generates a piezoelectric signal according to a load that is applied. A touch detecting unit detects contact with the pressure sensor. An acquirer acquires a piezoelectric output based on the piezoelectric signal. A rate-of-change calculator calculates a rate of change with respect to time of the piezoelectric output acquired within an arbitrary time range before a touch detection time when the touch detecting unit detects contact with the pressure sensor. An applied pressure calculator calculates applied pressure by correcting the piezoelectric output acquired after an end time of the time range used in the calculation of the rate of change using the rate of change. The apparatus enables precise measurement of applied pressure in a pressure sensor.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 6, 2018
    Assignee: NISSHA PRINTING CO., LTD.
    Inventors: Yuji Watazu, Naoto Imae, Eiji Kakutani, Keisuke Ozaki, Shinichi Hagihara, Junichi Shibata