Patents by Inventor Jun Idebuchi

Jun Idebuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100181598
    Abstract: Etch block layers having an etching rate smaller than that of a first semiconductor forming a semiconductor substrate are formed on the sidewalls of device isolation grooves by applying oblique ion implantation of Ox, N, or C to the semiconductor substrate including the first semiconductor. Embedded layers including a second semiconductor are selectively formed in recesses by epitaxial-growing the second semiconductor having a lattice constant larger than that of the first semiconductor in the recesses.
    Type: Application
    Filed: December 29, 2009
    Publication date: July 22, 2010
    Inventors: Tsutomu SATO, Jun Idebuchi, Yoshihisa Arie
  • Patent number: 7235490
    Abstract: A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask material on the working film, forming a resist pattern on the mask material, the mask material having a higher etching resistance for the working film than the resist pattern, transferring the pattern of the resist pattern onto the mask material, and etching the working film by using the mask material as a mask.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Sato, Seiji Nakagawa, Jun Idebuchi, Motoya Kishida, Shuichi Taniguchi, Tsuyoshi Shibata
  • Publication number: 20060084224
    Abstract: According to the present invention, there is provided a semiconductor devise comprising: a gate electrode formed via a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a source region and drain region formed in a surface portion of said semiconductor substrate on two sides of a channel region positioned below said gate electrode; a capacitor insulating film formed in the surface portion of said semiconductor substrate to cover an inner surface near a bottom portion of a trench formed adjacent to one of said source region and drain region; a capacitor electrode formed to be buried in said trench covered with said capacitor insulating film; an insulating film formed to cover an inner surface of said trench, which is not covered with said capacitor insulating film; a conductive layer containing a predetermined impurity and formed in said trench so as to be buried in a portion covered with said insulating film on said capacitor electrode; a surface connecting layer f
    Type: Application
    Filed: October 7, 2005
    Publication date: April 20, 2006
    Inventors: Shinya Watanabe, Jun Idebuchi
  • Publication number: 20040224512
    Abstract: A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask material on the working film, forming a resist pattern on the mask material, the mask material having a higher etching resistance for the working film than the resist pattern, transferring the pattern of the resist pattern onto the mask material, and etching the working film by using the mask material as a mask.
    Type: Application
    Filed: February 27, 2004
    Publication date: November 11, 2004
    Inventors: Yasuhiko Sato, Seiji Nakagawa, Jun Idebuchi, Motoya Kishida, Shuichi Taniguchi, Tsuyoshi Shibata