Patents by Inventor Jun Inagawa
Jun Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150163430Abstract: According to one embodiment, in the pixel array unit, pixels that accumulate photoelectrically converted electrical charge are arranged in a matrix state. The m address lines (m is an integer of two or more) are provided per row of the pixel array unit and select the pixel in a row direction. The vertical signal line transmits a pixel signal, which is read from the pixel, in a column direction.Type: ApplicationFiled: August 29, 2014Publication date: June 11, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shiroshi KANEMITSU, Atsuhiko NUNOKAWA, Miho IIZUKA, Jun INAGAWA
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Patent number: 8964069Abstract: According to one embodiment, an image processing device includes a defect correcting unit, a noise-reduction processing unit, and a selecting unit. The defect correcting unit executes defect correction on a target pixel. The defect correcting unit switches, according to the level of contrast determined concerning a plurality of peripheral pixels, a first correction value obtained through averaging processing for signal values of the peripheral pixels and a second correction value other than the first correction value.Type: GrantFiled: August 10, 2010Date of Patent: February 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shiroshi Kanemitsu, Kazuhiro Tabuchi, Takaaki Kawakami, Hirotoshi Aizawa, Jun Inagawa
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Patent number: 8305459Abstract: According to the Embodiments, an Image Processing apparatus includes a pixel interpolation processing unit. The pixel interpolation processing unit generates a sensitivity level value through addition of a first frequency range component of an image signal for a lacking color component and a second frequency range component of a frequency band lower than the first frequency range component. The pixel interpolation processing unit adjusts a ratio of the first frequency range component to be added to the second frequency range component.Type: GrantFiled: August 27, 2010Date of Patent: November 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Shiroshi Kanemitsu, Hirotoshi Alzawa, Takaaki Kawakami, Kazuhiro Tabuchi, Jun Inagawa
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Publication number: 20110122273Abstract: According to the Embodiments, an Image Processing apparatus includes a pixel interpolation processing unit. The pixel interpolation processing unit generates a sensitivity level value through addition of a first frequency range component of an image signal for a lacking color component and a second frequency range component of a frequency band lower than the first frequency range component. The pixel interpolation processing unit adjusts a ratio of the first frequency range component to be added to the second frequency range component.Type: ApplicationFiled: August 27, 2010Publication date: May 26, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shiroshi KANEMITSU, Hirotoshi Alzawa, Takaaki Kawakami, Kazuhiro Tabuchi, Jun Inagawa
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Publication number: 20110069209Abstract: According to one embodiment, an image processing device includes a defect correcting unit, a noise-reduction processing unit, and a selecting unit. The defect correcting unit executes defect correction on a target pixel. The defect correcting unit switches, according to the level of contrast determined concerning a plurality of peripheral pixels, a first correction value obtained through averaging processing for signal values of the peripheral pixels and a second correction value other than the first correction value.Type: ApplicationFiled: August 10, 2010Publication date: March 24, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Shiroshi KANEMITSU, Kazuhiro TABUCHI, Takaaki KAWAKAMI, Hirotoshi AIZAWA, Jun INAGAWA
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Patent number: 6061315Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.Type: GrantFiled: August 14, 1998Date of Patent: May 9, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Hiroshi Kobata
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Patent number: 5856962Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.Type: GrantFiled: April 10, 1997Date of Patent: January 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Hiroshi Kobata
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Patent number: 5856963Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.Type: GrantFiled: April 10, 1997Date of Patent: January 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Hiroshi Kobata
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Patent number: 5835464Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.Type: GrantFiled: December 19, 1997Date of Patent: November 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Hiroshi Kobata
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Patent number: 5828638Abstract: An apparatus for reproducing disc data of a compressed image type or another type includes a decompression circuit to decompress the disc data read from the disc in accordance with a reference clock signal. When the disc data is not image type data, the frequency of the reference clock is lowered to reduce power consumption.Type: GrantFiled: October 27, 1997Date of Patent: October 27, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Makoto Kubo
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Patent number: 5822289Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow. Writing information data read from the disc to the buffer memory is performed in response to a reproduction stage clock, and reading from the buffer memory is in response to a signal processing stage clock. The signal processing stage clock for reading information data may be derived from the reproduction stage clock.Type: GrantFiled: April 10, 1997Date of Patent: October 13, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Hiroshi Kobata
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Patent number: 5815476Abstract: An apparatus and a signal processing circuit for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow, and/or to reduce power consumption in a digital-to-analog converter. When the data to be read is ROM data, reading from the buffer memory is conducted in response to a varying frame clock signal, and the frequency of a reference clock signal to the digital-to-analog converter is reduced.Type: GrantFiled: October 27, 1997Date of Patent: September 29, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Makoto Kubo
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Patent number: 5729515Abstract: An apparatus and a signal processing circuit for reproducing data stored on a disc to prevent a buffer memory from experiencing overflow/underflow, and/or to reduce power consumption in a digital-to-analog converter. When the data to be read is ROM data, reading from the buffer memory is conducted in response to a varying frame clock signal, and the frequency of a reference clock signal to the digital-to-analog converter is reduced.Type: GrantFiled: May 25, 1995Date of Patent: March 17, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Yasuhiro Hayashi, Makoto Kubo
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Patent number: 5553041Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from going overflow/underflow. Writing information data read from the disc to the buffer memory is performed in synchronism with a reproduction stage clock signal, and reading from the buffer memory is in synchronism with a signal processing stage clock. The signal processing stage clock for reading information data from the buffer memory is changed in accordance with the amount of information data stored in the buffer memory for preventing interruptions in data reproduction.Type: GrantFiled: April 10, 1995Date of Patent: September 3, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Jun Inagawa, Masahide Nagumo, Kunihiko Kodama
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Patent number: 4860272Abstract: An apparatus for reproducing data stored on a disc in a plurality of tracks connected in a continuous spiral or separated in concentric tracks.Type: GrantFiled: September 21, 1987Date of Patent: August 22, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Meisei Nishikawa, Jun Inagawa, Takeshi Inagaki, Toshihiko Kaneshige, Yasuhiro Hayashi, Tadashi Kojima
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Patent number: 4608692Abstract: An error correction circuit in which an error location polynomial is determined on the basis of the code word of the code of a double correction BCH symbol in Galois field GF(2.sup.m), thereby determining the error location and error pattern necessary for the error correction. The error correction circuit includes: (a) means for generating a syndrome S.sub.i (i being an integer) from the code word: (b) first and second means for holding S.sub.1 and S.sub.0 out of the syndromes outputted from the syndrome generating means; (c) means for effecting the following calculation on the basis of the syndrome generated by the syndrome generating means:r.sub.3 =S.sub.2 S.sub.0 +S.sub.1.sup.2r.sub.2 =S.sub.3 S.sub.0 +S.sub.1 S.sub.2r.sub.1 =S.sub.3 S.sub.1 +S.sub.2.sup.2third means for holding r.sub.3 out of r.sub.3, r.sub.2 and r.sub.1 ; (d) means for judging whether r.sub.3 out of r.sub.3, r.sub.2 and r.sub.1 satisfy the condition: r.sub.3 .noteq.0 or r.sub.3 =0; (e) a control means for making, when the condition: r.Type: GrantFiled: September 6, 1984Date of Patent: August 26, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Masahide Nagumo, Tadashi Kojima, Jun Inagawa
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Patent number: 4574361Abstract: An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. "1" detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any "1" detector circuit detects "1" in response to output signals from a 2-input AND gate. When "1" is detected, a NOR gate supplies a signal of logical "0" to the AND gate, whereby the AND gate stops supplying output signals.Type: GrantFiled: March 10, 1983Date of Patent: March 4, 1986Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Jun Inagawa, Masahide Nagumo, Tadashi Kojima
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Patent number: 4567568Abstract: Data representing one element .alpha..sup.i of a Galois field GF(2.sup.m) are stored in a first linear shift register, and data representing another element .alpha..sup.j of the Galois field GF(2.sup.m) are stored in a second linear shift register. 2.sup.m elements of Galois field GF(2.sup.m) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter which includes a decoder and an encoder. The data representing element .alpha..sup.j are supplied from the second linear shift register to the decoder. If the data representing the reciprocal of element .alpha..sup.j are stored in the converter, they are read from the encoder. If they are not stored in the converter, the first linear shift register and the second linear shift register are shifted N times by control pulses generated by a NOR gate and an AND gate until any one of the reciprocal data are read from the encoder, whereby the register supplies data representing .Type: GrantFiled: March 10, 1983Date of Patent: January 28, 1986Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Jun Inagawa, Masahide Nagumo, Tadashi Kojima
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Patent number: 4498175Abstract: An error correcting system uses an error location polynomial which is defined by double correction BCH codes each consisting of the elements of a Galois field GF(2.sup.m), and thereby generates error locations .sigma..sub.1 and .alpha..sup.2 and error patterns e.sub.1 and 2.sub.2. The system has a first data processing system for performing only addition and multiplication to generate the error locations .sigma..sub.1 and .alpha..sup.2, and a second data processing system for performing only addition and multiplication to generate the error patterns e.sub.1 and 2.sub.2. The first data processing system comprises a syndrome generator, a memory, an arithmetic logic unit, registers, latch circuits, registers, adder circuits and a zero detector. The second data processing system comprises a gate circuit, latch circuits, an arithmetic logic unit, and the registers of a memory.Type: GrantFiled: September 30, 1982Date of Patent: February 5, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masahide Nagumo, Jun Inagawa, Tadashi Kojima
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Patent number: 4453260Abstract: A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.Type: GrantFiled: September 27, 1982Date of Patent: June 5, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Jun Inagawa, Masahide Nagumo, Tadashi Kojima