Patents by Inventor Jun Inasaka

Jun Inasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5792293
    Abstract: A method of fabricating a ceramic multi-layered wiring substrate, in which deformation of ceramic green sheets is prevented so that the probability of connection failure of through-holes is reduced, includes forming a ceramic green sheet on a carrier film and forming through-holes through the ceramic green sheet and the carrier film. The carrier film is used as a mask when the through-holes are filled with electrically conductive paste. The green sheet is attached onto a thick plate. The green sheets attached on the respective thick plates are sequentially adhered and laminated temporarily. The laminated green sheets form a ceramic green sheet lamination block which is sintered, resulting in a ceramic multi-layered wiring substrate.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5585138
    Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 17, 1996
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5460677
    Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: October 24, 1995
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5373110
    Abstract: When an external connection I/O pin which is formed on a multilayer ceramic circuit board is broken off together with a part of a ceramic substrate, an electrically conductive adhesive is filled in the area where the I/O pin broke and was removed, and together with standing a new pin in this place and connecting it electrically, the new pin is bridged and secured to the surrounding I/O pins using a fixation plate. In so doing, it is possible to restore the broken I/O pin to have the same electrical and mechanical characteristics as before.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5364276
    Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: November 15, 1994
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5271150
    Abstract: A method for fabricating a ceramic multi-layer substrate by a greensheet process includes a step of bonding an organic resin film on a ceramic greensheet cast on a carrier film; a step of forming a through-hole-on said ceramic greensheet in a state in which this ceramic greensheet retains one or both of said films and filling conductive paste in said through-hole by using one of said films as a mask; a step of removing one of said films, placing said ceramic greensheet on a stack of ceramic greensheets forming a base, forming a laminate assembly by applying pressure thereto, and removing the other of said films remaining in said assembly. It is possible to suppress the occurrence of deformation in dimensions of greensheets when they are processed and of displacement or misalignment when they are laminated.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: December 21, 1993
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 5136471
    Abstract: In a laminate wiring board having power source layers therein and provided with pins for signal input and output and pins for power supply, the power source layers are exposed at a side end of the wiring board, and pads for power supply are provided on the exposed side end.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: August 4, 1992
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 4980270
    Abstract: A printed circuit comprising a substrate, a first conductive circuit pattern thereon and an insulator on the first conductive circuit pattern. The insulator has a via hole which extends down to and is tapered toward the first conductive circuit pattern. A second conductive circuit pattern is formed on the side wall of the via hole and on a portion of the first conductive circuit pattern. The tapered via hole allows the second conductive circuit pattern to ensure excellent electrical contact with the first conductive circuit pattern.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: December 25, 1990
    Assignee: NEC Corporation
    Inventor: Jun Inasaka
  • Patent number: 4827083
    Abstract: A wiring substrate which may be sintered with a minimum of cracking of the via-fills has a wiring substrate with wiring layers made of paste containing palladium powder and silver powder composed of spherical silver particles and flake-like silver particles, insulating layers made of a ceramic material and through-hole wirings formed by the paste within the insulating layers to provide electrical connection between the wiring layers.
    Type: Grant
    Filed: April 7, 1988
    Date of Patent: May 2, 1989
    Assignee: NEC Corporation
    Inventors: Jun Inasaka, Shin-Ichi Hasegawa