Patents by Inventor Jun Iwamura

Jun Iwamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050245410
    Abstract: The residual amount of a solvent in a water soluble nonionic alkylene oxide resin is decreased in an apparatus including an evaporation vessel and a stirring blade which scrapes-up and coats resin solution onto the inner wall surface of the evaporation vessel. A water soluble nonionic alkylene oxide resin having a crystallization temperature of 10 to 60° C. is extruded to a predetermined thickness in a molten state, the extruded molten resin is brought into contact with a metal surface which is at the crystallization temperature (Tc) or lower, and the thereby solidified resin may be cut into pellets. The resin pellets preferably are of rectangular shape and prescribed dimensions. The resin may be pulverized in a pulverizer by shearing force between a rotary blade and a fixed blade. In the pulverizer, grains smaller than a predetermined size pass through the screen, while larger grains are again pulverized.
    Type: Application
    Filed: February 18, 2005
    Publication date: November 3, 2005
    Inventors: Masaki Tezuka, Hiroshi Tanaka, Takao Yokohashi, Takao Nishihata, Manabu Kikuta, Michiyuki Kono, Tetsuya Higashizaki, Kazuo Takei, Taketo Toba, Toshiaki Kuriyama, Izuho Okada, Fumihide Tamura, Ritsuo Kitada, Shigetaka Takamiya, Jun Iwamura, Takanori Murakami, Hiromoto Katsuyama, Teruki Matsushita
  • Patent number: 5045725
    Abstract: An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: September 3, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tohru Sasaki, Kazuyuki Omote, Jun Iwamura
  • Patent number: 4635037
    Abstract: An analog to digital converter comprising a data strobe terminal to which a signal is supplied upon the start of the converting operation, a delay circuit having a transistor with controlled conduction resistance and having its gate supplied with an analog input signal, an EX-OR gate having a first input terminal connected to the data strobe terminal and a second input terminal connected to the data strobe terminal through the delay circuit, an AND gate to which the output signal of the EX-OR gate and a clock pulse are supplied, and a counter for counting the output signal of the AND gate, whereby to produce the output of the counter as a digital signal.
    Type: Grant
    Filed: September 3, 1982
    Date of Patent: January 6, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Jun Iwamura
  • Patent number: 4491749
    Abstract: A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.
    Type: Grant
    Filed: March 23, 1983
    Date of Patent: January 1, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Jun Iwamura