Abstract: A method and a system for identifying authenticity of an electronic component is disclosed. The method may include obtaining chip data of an electronic component; extracting feature information of the chip data for reducing noise of the chip data; providing the feature information of the chip data to a trained deep learning model; and providing a user with an authenticity indication for the electronic component based on an output of the deep learning model. Other aspects, embodiments, and features are also claimed and described.

Abstract: A method and a system for identifying authenticity of an electronic component is disclosed. The method may include obtaining chip data of an electronic component: extracting feature information of the chip data for reducing noise of the chip data: providing the feature information of the chip data to a trained deep learning model; and providing a user with an authenticity indication for the electronic component based on an output of the deep learning model. Other aspects, embodiments, and features are also claimed and described.

Abstract: A method and system disable executable script in requested displayable content. Responsive to requesting displayable content, a non-executable code sequence and a mis-matched font file that maps a plurality of characters of the requested displayable content to the non-executable code sequence is received. The non-executable code sequence is displayed as a text string in accordance with the received mis-matched font file.

Abstract: A method and system provide and utilize obfuscated fonts for displayable content. Responsive to a request for displayable content having text, a text portion of the requested displayable content to be obfuscated is determined. For that text portion, obfuscated fonts are provided, by retrieving obfuscated fonts or by generating obfuscated fonts from a set of obfuscated glyphs created from a plurality of glyphs representative of a plurality of characters of the text portion of the displayable content. The obfuscated fonts can be created by assigning obfuscated glyphs of the set into the obfuscated fonts in accordance with one or more messages. The obfuscated fonts are mapped by assigning a value to each obfuscated glyph in the set that is different from an original value of the glyph.

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract: Methods of manufacturing a semiconductor device including metal gates are provided. The method may include forming a resistor pattern and a dummy gate electrode, which include polysilicon, and forming an impurity region adjacent to the dummy gate electrode. The method may further include replacing the dummy gate electrode with a gate electrode and then forming metal silicide patterns on the resistor pattern and the impurity region.

Abstract: Provided herein is a novel and useful method for evaluating the ability of compounds or agents to decrease the activity of microsomal prostaglandin E synthase or hematopoietic prostaglandin D synthase to produce their respective prostaglandin products.