Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.

Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Abstract: A method for repairing a single erasure in a Reed Solomon code in a system of a plurality of n storage nodes and a controller, wherein a content of each storage node is a codeword and each node stores a vector v. The method includes identifying a failed storage node; transmitting an index of the failed storage node to each surviving storage node; multiplying the content of each node i by a j-th component of a vector that is a permutation of elements of vector v that correspond to the surviving storage nodes; determining a trace map of the result and converting the result from an m×r bit representation into a reduced representation of r bits; reconstructing the content of the failed storage node from the reduced representation of each surviving node's content; and outputting the reconstructed content of the failed storage node.

Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A display device includes a display unit including pixels, a memory to store degradation data of the pixels, a group-setting portion to classify the pixels into degradation regions according to a degradation degree and based on the degradation data, perform a contour-simplifying process with respect to the degradation regions, classify the degradation regions into labeling regions according to proximity of adjacent ones of the degradation regions, and set one of the degradation regions as a reference region, a sensor to sense electric characteristics of the degradation regions and the reference region as they separately emit light, a compensation amount controller to compare the electric characteristics of the degradation regions with electric characteristics of the reference region, and calculate a per-position compensation data corresponding to a position of the labeling regions, and a converter to convert a first image data into a second image data based on the per-position compensation data.

Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n?kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns and Tj has k1?{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s where a=0 and b=Tjs, and cod

Abstract: A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an integer greater than or equal to 3. Each of the units of x bits is stored over a span of y memory cells of the MLC memory. Here, y is an integer greater than or equal to 2. At least one bit of each of the x bits is stored only partially in a first memory cell of the span of y memory cells and the at least one bit is also stored, only partially, in a second memory cell of the span of y memory cells such that the at least one bit cannot be interpreted without reading both the first and second memory cell of the span of y memory cells.

Abstract: A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

Abstract: An application specific integrated circuit (ASIC) tangibly encodes a program of instructions executable by the integrated circuit to perform a method for fast Chase decoding of generalized Reed-Solomon (GRS) codes. The method includes using outputs of a syndrome-based hard-decision (HD) algorithm to find an initial Groebner basis G for a solution module of a key equation, upon failure of HD decoding of a GRS codeword received by the ASIC from a communication channel; traversing a tree of error patterns on a plurality of unreliable coordinates to adjoin a next weak coordinate, where vertices of the tree of error patterns correspond to error patterns, and edges connect a parent error pattern to a child error pattern having exactly one additional non-zero value, to find a Groebner basis for each adjoining error location; and outputting an estimated transmitted codeword when a correct error vector has been found.

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Abstract: A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before the each input bit. The method further includes selecting a plurality of survivor bits from among the decoded input bits, and storing the selected survivor bits in the memory module in a binary tree configuration. The number of edges in each level of the binary tree configuration does not exceed the list size.

Abstract: A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.

Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.