Abstract: A battery module includes: a first battery cell assembly having at least one battery cell; a second battery cell assembly spaced apart from the first battery cell assembly by a predetermined distance and having at least one battery cell; a bottom plate configured to integrally support the second battery cell assembly and the first battery cell assembly; and a top plate disposed above the bottom plate to integrally cover the first battery cell assembly and the second battery cell assembly.

Abstract: A battery module and a battery pack having a module housing capable of effectively increasing an energy density while enhancing the heat dissipation efficiency, includes a cell assembly having a plurality of secondary batteries; and a module housing having at least one sidewall and configured to accommodate the cell assembly in an inner space defined by the sidewall. The sidewall has at least one coolant flow path, and at least one injection hole is formed in an outer surface of the sidewall so as to extend to and communicate with the inner space.

Abstract: A battery module allows improved manufacturing due to easy electric connection between a bus bar assembly and secondary batteries. The battery module includes a cell stack formed by stacking a plurality of secondary batteries having electrode leads on each other in a stacking direction; and a bus bar assembly including a connection bus bar contacting two or more of the electrode leads of the plurality of secondary batteries and having an insert groove formed so that at least one of the electrode leads is inserted therein, and a coupling bus bar coupled to the connection bus bar and having a rear surface formed to press the at least one of the electrode leads inserted in the insert groove.

Abstract: An etch stop layer is formed on a lower wiring. An interlayer insulating film covers the lower wiring and the etch stop layer. A via exposes an upper surface of the etch stop layer, in the interlayer insulating film. A first filler is formed in the via. The first filler is etched to a first filler pattern. A second filler is formed on the first filler pattern and is etched to a second filler pattern. A trench is formed by etching the interlayer insulating film. The first and second filler patterns are etched during the forming of the trench to form a residual filler pattern. The residual filler pattern and the etch stop layer are removed and a wiring structure is formed electrically connected to the lower wiring. The via includes lower and upper portions and the trench includes the upper portion of the via.

Abstract: A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

Abstract: A battery module which includes a battery cell stack in which a plurality of battery cells are stacked; and a housing configured to accommodate the battery cell stack, wherein a disassembling guide for disassembling the housing is formed at the housing.

Abstract: An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

Abstract: A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Abstract: A lithium-sulfur battery includes: a substrate; a composite cathode disposed on the substrate; a solid-state electrolyte disposed on the composite cathode; and a lithium anode disposed on the solid-state electrolyte, such that the composite cathode comprises: active elemental sulfur, conductive carbon, sulfide electrolyte, and ionic liquid.

Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: A battery module includes a heat-shrinkable tube serving as a module housing. The battery module includes a cell assembly having a plurality of pouch-type secondary batteries; a bus bar assembly having a bus bar frame and a bus bar mounted to an outer surface of the bus bar frame; and a heat-shrinkable tube formed to be shrunk by heat and configured so that the cell assembly is located therein, the heat-shrinkable tube being provided to surround a side surface of the cell assembly and a portion of the bus bar assembly.

Abstract: Disclosed herein is a battery charging system of an electric vehicle charging station, the battery charging system including: a charging unit configured to supply an electrical power to charge a battery of an electric vehicle; a charging cable connected to the charging unit and having a connector attached thereto to correspond to an inlet of the electric vehicle; and a cooling unit disposed at a location where the electric vehicle is parked in charging to supply a cooling air toward the battery of the electric vehicle.

Abstract: A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

Abstract: The present disclosure relates to a substrate processing apparatus and a substrate processing method using the same, and more particularly, to a substrate processing apparatus that is capable of improving a flow of a process gas that is participated in a substrate processing process and a substrate processing method using the same.

Abstract: The present invention relates to microstructure formulation techniques for botulinum toxin. The microstructure formulation techniques for botulinum toxin according to the present invention make it possible to precisely control the concentration of botulinum toxin and to alleviate the pain occurring when botulinum toxin is administered into the human body, and also enable botulinum toxin to be accurately administered to a desired position. Thus, the present invention is expected to greatly contribute to the safe and convenient medical use of botulinum toxin.

Abstract: A touch input device capable of detecting a pressure of a touch on a touch surface may be provided that includes: a display module; and a pressure sensor which is disposed at a position where a distance between the pressure sensor and a reference potential layer is changeable according to the touch on the touch surface. The distance is changeable according to a pressure magnitude of the touch. The pressure sensor outputs a signal including information on a capacitance which is changed according to the distance. The pressure sensor includes a plurality of electrodes to form a plurality of channels. The pressure magnitude of the touch is detected on the basis of a change amount of the capacitance detected in each of the channels. According to the embodiment of the present invention, it is possible to provide a pressure sensor for pressure detection, a touch input device including the same, and a pressure detection method using the same.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: Disclosed is a battery module, which includes a cell assembly composed of a plurality of cells, and a frame assembly having a bottom plate supporting the cell assembly from a lower portion, a side plate perpendicular to the bottom plate and disposed adjacent to an outermost side of the cell assembly, and a top plate covering an upper portion of the cell assembly, wherein a groove forming an external air inflow space between the side plate and the cell assembly is formed at the side plate to elongate in a length direction thereof.

Abstract: The present invention relates to a nanovesicle comprising a heterodimeric G-protein coupled receptor, a method for preparing the nanovesicle, a field effect transistor-based taste sensor comprising the nanovesicle, and a method for manufacturing the taste sensor. The field effect transistor based taste sensor functionalized by the nanovesicle comprising the heterodimer G-protein coupled receptor according to the present invention has excellent sensitivity and selectivity and may highly specifically detect a sweet taste substance in real time, by using the heterodimeric G-protein coupled receptor and the nanovesicle comprising the same.

Abstract: A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.