Abstract: In a frequency synthesizer, a first, constant frequency divider is connected to a reference frequency oscillator, and a second, variable frequency divider is connected to a voltage-controlled oscillator. A phase difference is detected by a phase detector between the frequency dividers and a first output pulse or a second output pulse is produced when the second frequency divider is leading or lagging the first frequency divider. A charge pump integrates the first and second output pulses to supply a phase difference signal to a lowpass filter which drives rates the voltage-controlled oscillator. An initial phase difference which occurs between the frequency dividers immediately after they are energized is detected and one of the frequency dividers is reset with the detected phase difference to align their phase. As long as the initial phase difference is detected, the passages of the first and second output pulses to the charge pump are blocked.

Abstract: A PLL frequency synthesizer for realizing high-speed operation in a frequency synthesizer having a small channel interval .DELTA.f. There are provided n-number of phase comparators, feedback frequency dividers, and reference signal frequency dividers, and a timing generating section for outputting a signal causing each of the frequency dividers to become enabled every cycle of n.times..DELTA.f. An OR gate for superposing each phase comparison signal. Each phase comparison signal is sent to a charge pump after a cycle of n.times..DELTA.f, and the reference frequency is capable of being raised to n times the channel interval .DELTA.f. Further, a control section monitors lock detection of each phase comparator, thus implementing voltage control of each phase comparison system. When the synthesizer arrives at convergence-synchronization, the power sources to all systems are turned OFF except for the phase comparison system initiating the lock signal.

Abstract: A phase-locked loop (PLL) frequency synthesizer is described that both reduces frequency channel spacing and accelerates convergence, and moreover, suppresses the occurrence of spurious noise. A frequency dividing circuit of the PLL frequency synthesizer is composed of a plurality of frequency dividers. By means of a timing generation circuit that is operated by frequency signals from an external oscillation circuit, each of frequency dividers are sequentially delayed by each cycle, and the output of these frequency dividers is taken as feedback signals of the phase comparator of the phase-locked loop.

Abstract: In a frequency synthesizer of a TDMA cellular communication mobile unit, a reference pulse is supplied from a reference pulse source to a phase comparator whose output is coupled through an open/close loop mode switch to a loop filter which is connected to a VCO. A frequency divider produces a submultiple of the VCO frequency and supplies its output to the phase comparator. For power savings purposes, a controller first activates the reference pulse source and the frequency divider and operates the switch to establish a connection between the phase comparator and the loop filter. The controller then operates the frequency divider so that a channel is established between the mobile unit and a first cell site station, and then operates the switch to clear the connection and deactivates the reference pulse source and the frequency divider to allow signals to be exchanged between the mobile unit and the first cell site station during a transmit/receive slot of the channel in a power saving mode.

Abstract: During transmit and receive slots of a TDMA frame, a reference pulse source (31) is made inactive for power savings purposes, and during an idle slot of the frame it is rendered active to supply pulses to a phase alignment circuit (32) where initial phase alignment is established between an output of a frequency divider (37) and the reference pulse. Phase-aligned signals are supplied to a phase comparator (33), the output of which is coupled to a switched filter bank (35) during the idle slot to cause a selected loop filter to develop a voltage according to the output of the phase comparator (33) to drive a voltage controlled oscillator (36) to generate a local carrier for allowing a channel switching to be effected for a possible hand-off. The connection between the phase comparator (33) and the filter bank (35) is cut off during the transmit and receive slots to maintain that voltage for a closed-loop operation during the next idle slot.

Abstract: A local oscillation frequency synthesizer has first and second phase locked loop synthesizers for providing first and second oscillation frequency signals. The local oscillation frequency synthesizer also includes a controller which increases a frequency of the first oscillation frequency signal by a predetermined frequency amount corresponding to the change-over of channels and thereafter decreases the frequency of the first oscillation frequency signal to its original frequency. The controller also increases a frequency of the second oscillation frequency signal after the increase of the first oscillation frequency signal without thereafter decreasing the second oscillation frequency signal to its original frequency.

Abstract: A control voltage coarse adjustment circuit including a D/A converter voltage generator is provided on a load side of a capacitor in a loop filter included in a phase locked loop. For this structure, a coarsely adjusted voltage is generated to be added to a voltage which is generated by the capacitor of the loop filter for the switch-over of channels during a communication frame. The added voltages are applied to a voltage controlled oscillator to change a frequency for the switch-over of channels. Consequently, the charge and discharge of the capacitor is carried out in a short time to suppress the influence of dielectric absorption current. Thus, the intermittent operation of the phase locked loop in which the phase locked loop is closed and opened intermittently is carried out for the saving of electric power consumption, and a carrier frequency is stabilized in the open phase locked loop by an electric charge voltage of the capacitor in the loop filter.

Abstract: A local oscillating frequency synthesizer includes a pair of synthesizers, one being used for synchronizing the frequencies of the communication channels used for the transmission and reception slots, and the other for synchronizing the frequencies when the electric field level of the other station is monitored and information is read out between idle slots other than the transmission and reception slots. Therefore, without using a high speed frequency switching synthesizer such as a direct digital synthesizer or the like, the synchronization of the frequencies by switching can be achieved in a short period of time and a local oscillating portion which is low in power consumption can be obtained.