Patents by Inventor Jun-Jung Kim
Jun-Jung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951207Abstract: The present invention provides a stable liquid pharmaceutical formulation containing: an antibody or its antigen-binding fragment; a surfactant; a sugar or its derivative; and a buffer. The stable liquid pharmaceutical formulation according to the present invention has low viscosity while containing a high content of the antibody, has excellent long-term storage stability based on excellent stability under accelerated conditions and severe conditions, and may be administered subcutaneously.Type: GrantFiled: June 28, 2017Date of Patent: April 9, 2024Assignee: Celltrion Inc.Inventors: Joon Won Lee, Won Yong Han, Su Jung Kim, Jun Seok Oh, So Young Kim, Su Hyeon Hong, Yeon Kyeong Shin
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Publication number: 20240101088Abstract: A braking system includes a hydraulic brake including a first hydraulic brake provided on one of a front wheel and a rear wheel of a vehicle and a second hydraulic brake provided on the other of the front wheel and the rear wheel of the vehicle, a main braking force adjusting device configured to control braking hydraulic pressure supplied to the first hydraulic brake and the second hydraulic brake, and an auxiliary braking force adjusting device configured to directly control braking hydraulic pressure of the first hydraulic brake when a failure occurs in the main braking force adjusting device, wherein the first hydraulic brake is connected to the main braking force adjusting device via the auxiliary braking force adjusting device.Type: ApplicationFiled: January 12, 2023Publication date: March 28, 2024Applicants: Hyundai Motor Company, Kia CorporationInventors: Ho Jung NAM, Joo Beom KIM, Jun Ho PARK
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Publication number: 20240086135Abstract: An electronic device is provided that includes a first display and a second display. The electronic device also includes a processor configured to allocate a first set of resources to the first display and a second set of resources to the second display. The first set of resources is different from the second set of resources. Each of the first set of resources and the second set of resources includes one or more of at least one available hardware resource and at least one available software resource.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Inventors: Duk Ki HONG, Hyuk KANG, Jeong Hun KIM, Jae Bong YOO, Kyung Soo LIM, Jun Hak LIM, Min Gyew KIM, Na Jung Seo
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Patent number: 10229876Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.Type: GrantFiled: March 17, 2016Date of Patent: March 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Jung Kim, Young-Bae Kim, Jong-Sam Kim, Jin-Hyeung Park, Jeong-Hoon Ahn, Hyeok-Sang Oh, Kyoung-Woo Lee, Hyo-Seon Lee, Suk-Hee Jang
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Patent number: 9716043Abstract: In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.Type: GrantFiled: June 21, 2016Date of Patent: July 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyeung Park, Yeon-Joo Kim, In-Hwan Kim, Jun-Jung Kim, Kyoung-Pil Park, Jeong-Hoon Ahn, Sang-Chul Lee, Joon-Nyung Lee, Hyo-Seon Lee
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Publication number: 20160379891Abstract: In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.Type: ApplicationFiled: June 21, 2016Publication date: December 29, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: JIN-HYEUNG PARK, Yeon-Joo Kim, In-Hwan Kim, Jun-Jung Kim, Kyoung-Pil Park, Jeong-Hoon Ahn, Sang-Chul Lee, Joon-Nyung Lee, Hyo-Seon Lee
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Publication number: 20160343660Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.Type: ApplicationFiled: March 17, 2016Publication date: November 24, 2016Inventors: Jun-Jung KIM, Young-Bae KIM, Jong-Sam KIM, Jin-Hyeung PARK, Jeong-Hoon AHN, Hyeok-Sang OH, Kyoung-Woo LEE, Hyo-Seon LEE, Suk-Hee JANG
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Patent number: 8865486Abstract: The present application relates to a method for fabricating an organic light emitting display device, comprising: forming a drive thin film transistor on a substrate at a non-light emission region; forming a protective layer on the substrate; forming a color filter on the protective layer; forming a planarizing layer on a protective layer including the color filter; selectively removing the protective layer and the light compensating layer to form a first drain contact hole which exposes a drain electrode of the drive thin film transistor; forming a light compensating layer on the planarizing layer to have a second drain contact hole which exposes the first contact hole, and a dummy hole to expose the planarizing layer; and forming an organic light emitting element on the light compensating layer to be in contact with the drain electrode through the first and second drain contact holes.Type: GrantFiled: April 22, 2014Date of Patent: October 21, 2014Assignee: LG Display Co., Ltd.Inventors: Jun-Jung Kim, Hee-Suk Pang
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Publication number: 20140227810Abstract: The present application relates to a method for fabricating an organic light emitting display device, comprising: forming a drive thin film transistor on a substrate at a non-light emission region; forming a protective layer on the substrate; forming a color filter on the protective layer; forming a planarizing layer on a protective layer including the color filter; selectively removing the protective layer and the light compensating layer to form a first drain contact hole which exposes a drain electrode of the drive thin film transistor; forming a light compensating layer on the planarizing layer to have a second drain contact hole which exposes the first contact hole, and a dummy hole to expose the planarizing layer; and forming an organic light emitting element on the light compensating layer to be in contact with the drain electrode through the first and second drain contact holes.Type: ApplicationFiled: April 22, 2014Publication date: August 14, 2014Applicant: LG DISPLAY CO., LTD.Inventors: Jun-Jung KIM, Hee-Suk PANG
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Patent number: 8742436Abstract: The present invention relates to an organic light emitting display device which can prevent a light compensation layer from cracking and a method for fabricating the same.Type: GrantFiled: September 25, 2012Date of Patent: June 3, 2014Assignee: LG Display Co., Ltd.Inventors: Jun-Jung Kim, Hee-Suk Pang
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Patent number: 8338245Abstract: An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.Type: GrantFiled: March 14, 2008Date of Patent: December 25, 2012Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: Jae Gon Lee, Jong Ho Yang, Victor Chan, Jun Jung Kim
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Patent number: 8227308Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.Type: GrantFiled: December 28, 2009Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park, Jun-Jung Kim, Tae-Gyun Kim
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Publication number: 20110156110Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Jun-jung Kim, Sang-jine Park, Min-ho Lee, Thomas W. Dyer, Sunfei Fang, O-sung Kwon, Johnny Widodo
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Patent number: 7923365Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.Type: GrantFiled: October 17, 2007Date of Patent: April 12, 2011Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Infineon Technologies AGInventors: Jun-jung Kim, Sang-jine Park, Min-ho Lee, Thomas W. Dyer, Sunfei Fang, O-sung Kwon, Johnny Widodo
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Patent number: 7790622Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.Type: GrantFiled: July 14, 2007Date of Patent: September 7, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: Kyoung Woo Lee, Ja Hum Ku, Jun Jung Kim, Chong Kwang Chang, Min-Chul Sun, Jong Ho Yang, Thomas W. Dyer
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Patent number: 7785950Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.Type: GrantFiled: November 10, 2005Date of Patent: August 31, 2010Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd, Chartered Semiconductor Manufacturing LtdInventors: Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh
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Publication number: 20100167533Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.Type: ApplicationFiled: December 28, 2009Publication date: July 1, 2010Inventors: Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park, Jun-Jung Kim, Tae-Gyun Kim
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Patent number: 7612414Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.Type: GrantFiled: March 29, 2007Date of Patent: November 3, 2009Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Xiangdong Chen, Jun Jung Kim, Young Gun Ko, Jae-Eun Park, Haining S. Yang
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Patent number: 7585773Abstract: A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.Type: GrantFiled: November 3, 2006Date of Patent: September 8, 2009Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Sunfei Fang, Jun Jung Kim, Thomas Dyer