Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: A liquid crystal display comprising: a transparent insulating substrate; a plurality of gate bus lines and a plurality of data bus lines arranged normal to the plurality of gate bus lines on the transparent insulating substrate, wherein a unit pixel region is defined by a region bounded by a pair of gate bus lines and a pair of data bus lines; a first electrode arranged parallel to the gate bus line within the unit pixel region; a first insulating layer formed on the first electrode; a second electrode formed at a selected portion of upper surface of the first insulating layer; a first transparent electrode formed within the unit pixel region, the first transparent electrode being apart by a selected distance from the second electrode, and being in contact with the first electrode; a second insulating layer formed on upper surface of the first insulating layer including the first transparent electrode and the second electrode; a second transparent electrode formed on the second insulating layer, the second tr