Patents by Inventor Jun Keat Lee

Jun Keat Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip-on-lead package and method of forming
    Patent number: 9018044
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING
    Publication number: 20140248747
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Application
    Filed: May 9, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • Chip-on-lead package and method of forming
    Patent number: 8759978
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING
    Publication number: 20130168866
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 4, 2013
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee