Patents by Inventor Jun-Ki Choi

Jun-Ki Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162494
    Abstract: The present disclosure relates to an electrolyte solution for a lithium secondary battery capable of improving the output and lifespan characteristics at high temperature of a lithium secondary battery, and a lithium secondary battery including the same. An electrolyte solution for a lithium secondary battery includes a lithium salt, a solvent, and a functional additive, wherein the functional additive includes a negative-electrode film additive, which is silver p-toluenesulfonate.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 16, 2024
    Inventors: Ko Eun Kim, Yoon Sung Lee, Sung Ho Ban, Jun Ki Rhee, Hui Beom Nam, Hyeon Gyu Moon, Nam-Soon Choi
  • Publication number: 20240153435
    Abstract: A display driving circuit is provided. The display driving circuit includes a timing controller configured to output image data and a source control signal, a first source driver circuit configured to output first source data of the image data by activating a plurality of first data lines in accordance with the source control signal, the first data lines having a first output spreading time, a second source driver circuit configured to output second source data of the image data by activating a plurality of second data lines in accordance with the source control signal, the second data lines having a second output spreading time, and a third source driver circuit configured to output third source data of the image data by activating a plurality of third data lines in accordance with the source control signal, the third data lines having a third output spreading time, wherein the first output spreading time, the second output spreading time and the third output spreading time do not overlap.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 9, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hong PARK, Oh Jae KWON, Suk Ki MIN, Taek Kyun SHIN, Doo-Hee LIM, Young Ho CHOI
  • Publication number: 20240154042
    Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.
    Type: Application
    Filed: July 17, 2023
    Publication date: May 9, 2024
    Inventors: Jun Ki PARK, Wan Don KIM, Jeong Hyuk YIM, Hyo Seok CHOI, Sung Hwan KIM
  • Publication number: 20240136368
    Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Seon Young CHOI, Jae Hyung CHO, Jee Hoon SIM, Jun Ki JEONG
  • Publication number: 20240074050
    Abstract: A printed circuit board according to an embodiment includes: an insulation layer including a recess portion; and a connection pad disposed on the recess portion of the insulation layer and protruded from the recess portion, wherein the connection pad may include a protrusion and a concave portion that is lower than the protrusion, and a surface height of the protrusion of the connection pad may be substantially the same as or less than a surface height of the insulation layer.
    Type: Application
    Filed: May 30, 2023
    Publication date: February 29, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jun Ki Min, Seong Ho Choi
  • Patent number: 7902632
    Abstract: A pumping MOS capacitor includes a substrate which is conductive and includes an irregular surface, a dielectric film formed along the irregular surface of the substrate and a gate formed on the dielectric film.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Ki Choi
  • Publication number: 20090321802
    Abstract: A pumping MOS capacitor includes a substrate which is conductive and includes an irregular surface, a dielectric film formed along the irregular surface of the substrate and a gate formed on the dielectric film.
    Type: Application
    Filed: December 3, 2008
    Publication date: December 31, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventor: Jun-Ki CHOI