Patents by Inventor Jun-Ki Kang

Jun-Ki Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118182
    Abstract: A glass stress test method includes breaking a glass, analyzing a shape of a crack of a broken portion of the glass in a plan view, finding a breakage origin of the glass based on the shape of the crack in the plan view, analyzing a cross-section of the breakage origin, and calculating a stress of the glass based on a cross-sectional analysis result of the breakage origin. The stress of the glass is calculated as a value proportional to a floor constant defined by a condition of a floor surface disposed when the glass is broken.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Inventors: Min Ki KIM, Ji Hyun KO, Yong Kyu KANG, Jinsu NAM, Hyun Seung SEO, JUN HO LEE
  • Publication number: 20240083384
    Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 14, 2024
    Applicants: Hyundai Motor Company, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.
    Inventors: Sang Soo LEE, Chan Ho JUNG, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Deok Soo LIM, Sang Do PARK, In Sun BAEK, Sin Chan YANG, Chan Ki CHO, Myung Soo LEE, Jae Yong JANG, Jun Sik HWANG, Ho Sung KANG, Hae Dong KWAK, Hyun Tak KO
  • Patent number: 11923426
    Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Won Kang, Tae-Yeol Kim, Jeong Ik Kim, Rak Hwan Kim, Jun Ki Park, Chung Hwan Shin
  • Patent number: 11880269
    Abstract: Disclosed herein are a method for generating Gaussian error data using flash memory and an apparatus using the method. The method includes receiving a request to generate Gaussian error data and delivering an operation command to flash memory; generating Gaussian error noise based on a threshold voltage that is generated when the flash memory performs the operation command; and generating Gaussian error data so as to correspond to the Gaussian error noise and providing the same.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 23, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Moon-Seok Kim, Bong-Soo Lee, Jun-Ki Kang, Ki-Hong Kim
  • Patent number: 11783894
    Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: October 10, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Moon-Seok Kim, Bong-Soo Lee, Jun-Ki Kang, Ki-Hong Kim
  • Publication number: 20220374302
    Abstract: Disclosed herein are a method for generating Gaussian error data using flash memory and an apparatus using the method. The method includes receiving a request to generate Gaussian error data and delivering an operation command to flash memory; generating Gaussian error noise based on a threshold voltage that is generated when the flash memory performs the operation command; and generating Gaussian error data so as to correspond to the Gaussian error noise and providing the same.
    Type: Application
    Filed: August 26, 2021
    Publication date: November 24, 2022
    Inventors: Moon-Seok KIM, Bong-Soo LEE, Jun-Ki KANG, Ki-Hong KIM
  • Publication number: 20220366975
    Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.
    Type: Application
    Filed: August 26, 2021
    Publication date: November 17, 2022
    Inventors: Moon-Seok KIM, Bong-Soo LEE, Jun-Ki KANG, Ki-Hong KIM
  • Patent number: 9158147
    Abstract: A liquid crystal display device includes first and second substrates and a liquid crystal layer interposed therebetween; a gate line, a data line and a common line over the first substrate in the display area; a thin film transistor connected to the gate line and the data line; a color filter layer over the thin film transistor; a first passivation layer over the color filter layer; an auxiliary common line, inner common electrodes and pixel electrodes over the first passivation layer, wherein the auxiliary common line includes a vertical portion and a horizontal portion, the inner common electrodes extend from the horizontal portion, and the pixel electrodes alternate the inner common electrodes; a light blocking pattern in the non-display area, wherein the light blocking pattern includes the same materials as the color filter layer.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 13, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Jong-Woo Kim, Chang-Ho Oh, Won-Hyung Yoo, Sang-Yoon Paik, Jun-Ki Kang
  • Patent number: 9049004
    Abstract: A low-power encryption apparatus and method are provided. The low-power encryption apparatus includes a mask value generation unit, a mask value application unit, a round key application unit, a mask operation unit, a shift operation unit, and a shift operation correction unit. The mask value generation unit generates a mask value M having the same bit length as input round function values. The mask value application unit generates first masking round function values by applying the mask value M. The round key application unit generates second masking round function values by applying round key values. The mask operation unit generates third masking round function values by performing a mask addition operation. The shill operation unit generates fourth masking round function values by performing a circular shift operation. The shift operation correction unit generates output round function values by performing an operation using the mask value M.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 2, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jun-Ki Kang, Sang-Han Lee, Bong-Soo Lee, Seok Ryu, Jung-Chul Ahn, Jung-Gil Park
  • Publication number: 20140153725
    Abstract: A low-power encryption apparatus and method are provided. The low-power encryption apparatus includes a mask value generation unit, a mask value application unit, a round key application unit, a mask operation unit, a shift operation unit, and a shift operation correction unit. The mask value generation unit generates a mask value M having the same bit length as input round function values. The mask value application unit generates first masking round function values by applying the mask value M. The round key application unit generates second masking round function values by applying round key values. The mask operation unit generates third masking round function values by performing a mask addition operation. The shill operation unit generates fourth masking round function values by performing a circular shift operation. The shift operation correction unit generates output round function values by performing an operation using the mask value M.
    Type: Application
    Filed: June 28, 2013
    Publication date: June 5, 2014
    Inventors: Jun-Ki KANG, Sang-Han LEE, Bong-Soo LEE, Seok RYU, Jung-Chul AHN, Jung-Gil PARK
  • Publication number: 20130033654
    Abstract: A liquid crystal display device includes first and second substrates and a liquid crystal layer interposed therebetween; a gate line, a data line and a common line over the first substrate in the display area; a thin film transistor connected to the gate line and the data line; a color filter layer over the thin film transistor; a first passivation layer over the color filter layer; an auxiliary common line, inner common electrodes and pixel electrodes over the first passivation layer, wherein the auxiliary common line includes a vertical portion and a horizontal portion, the inner common electrodes extend from the horizontal portion, and the pixel electrodes alternate the inner common electrodes; a light blocking pattern in the non-display area, wherein the light blocking pattern includes the same materials as the color filter layer.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Applicant: LG DISPLAY CO., LTD.,
    Inventors: Jong-Woo Kim, Chang-Ho Oh, Won-Hyung Yoo, Sang-Yoon Paik, Jun-Ki Kang