Patents by Inventor Jun Kitano

Jun Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200354100
    Abstract: A product transfer apparatus includes a product suction pad part having a suction cup part capable of sucking a plate-like product, a transfer base whose lower part has the product suction pad part, and a label suction part having a label pad, which is able to suck a label to be pasted to the product, and an up-down function of moving the label pad up and down between a position upper than and a position lower than the position of a front end of the suction cup part.
    Type: Application
    Filed: November 8, 2018
    Publication date: November 12, 2020
    Applicant: AMADA CO., LTD.
    Inventors: Jun HIRONO, Koji TSUDA, Hideto FUKUSHIGE, Kuniaki ABE, Ryoma KITANO
  • Publication number: 20200208601
    Abstract: A compressed self-ignition type internal combustion engine includes a fuel injection nozzle provided such that a plurality of injection holes are exposed from a cylinder head of the internal combustion engine to a combustion chamber, and a plurality of hollow ducts configured such that an inlet and an outlet are exposed to the combustion chamber. The plurality of ducts are configured such that each fuel spray injected from the plurality of injection holes of the fuel injection nozzle passes from the inlet to the outlet. The internal combustion engine includes a heating device for heating at least one of the plurality of ducts.
    Type: Application
    Filed: December 2, 2019
    Publication date: July 2, 2020
    Inventors: Jun KAWAKAMI, Koji KITANO
  • Publication number: 20200199518
    Abstract: An incubator which can uniformly maintain a temperature/humidity in a culture chamber and prevent dew condensation from occurring in the culture chamber is provided. Further, an incubator which raises an air pressure in a culture chamber higher than that of the external environment to maintain an aseptic environment and prevents water vapor to be supplied from adversely affecting the inner aseptic environment is provided. An incubator includes a culture chamber including an insulated door and insulated wall, circulating means for circulating air in the culture chamber, temperature regulating means for regulating a temperature of the air in the culture chamber, and humidifying means for humidifying the air in the culture chamber.
    Type: Application
    Filed: May 9, 2018
    Publication date: June 25, 2020
    Inventors: Koji Kawasaki, Hideo Nishiwaki, Daisuke Kakuda, Jun Masudome, Yukihiro Yazaki, Zhiqiang Guo, Tsukasa Kitano
  • Patent number: 5475692
    Abstract: Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: December 12, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Susumu Hatano, Jun Kitano, Kenji Nishimoto, Shin'ichi Ikenaga, Masayasu Kawamura, Yasushi Takahashi, Takeshi Wada, Michihiro Mishima, Fujio Yamamoto
  • Patent number: 5473577
    Abstract: In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: December 5, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Jun Miyake, Jun Kitano
  • Patent number: 5283886
    Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: February 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Nishii, Kunio Uchiyama, Hirokazu Aoki, Kanji Oishi, Jun Kitano, Susumu Hatano