Abstract: A radius endmill suppressing chatter vibration includes a circular arc edge provided on an outer peripheral side of a distal end portion of a tool body, and a nose (R) angle (?r) that is an angular range in which the circular arc edge is formed in a vertical section including a central axis line of the tool body and which is equal to or less than 30°. The circular arc edge is formed, as a circular arc edge for a bottom surface, from a position having a tangential line in a direction that perpendicularly intersects the central axis line to a side surface in a bottom surface of the distal end portion of the tool body in a vertical section. A nose (R) height (Hr) that is a dimension of the circular arc edge in the direction of the central axis line is equal to or less than 0.75 mm.

Abstract: A continuous decontamination-and-sterilization device possessing high efficiency, reliability, and safety of operation to treat external surfaces of a package that is conveyed to a sterile working chamber. A decontamination chamber decontaminates (with a decontamination agent) bottom and lateral external surfaces of the package conveyed by a first conveyance, with an upper surface seal portion of the package being sealed. An aeration chamber removes residue of decontamination agent from an external surface of the package while the package is conveyed by a second conveyance means. A sterilization chamber sterilizes the upper surface seal portion of the package by irradiating electron beams as the package is conveyed by a third conveyance means, with the bottom or lateral external surface of the package being supported.

Abstract: A continuous decontamination-and-sterilization device possessing high efficiency, reliability, and safety of operation to treat external surfaces of a package that is conveyed to a sterile working chamber. A decontamination chamber decontaminates (with a decontamination agent) bottom and lateral external surfaces of the package conveyed by a first conveyance, with an upper surface seal portion of the package being sealed. An aeration chamber removes residue of decontamination agent from an external surface of the package while the package is conveyed by a second conveyance means. A sterilization chamber sterilizes the upper surface seal portion of the package by irradiating electron beams as the package is conveyed by a third conveyance means, with the bottom or lateral external surface of the package being supported.

Abstract: Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Abstract: In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.

Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.