Patents by Inventor Jun Komiyama

Jun Komiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605716
    Abstract: The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 ?·cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 ?m, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm3 and a specific resistance of 100 to 1000 ?·cm.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 14, 2023
    Assignee: COORSTEK KK
    Inventors: Hiroshi Oishi, Jun Komiyama, Yoshihisa Abe, Kenichi Eriguchi
  • Patent number: 11509983
    Abstract: Provided is an audio reproduction device that includes first and second speaker supports that have a lid shape and are provided on a case in an openable and closable manner, a sensor that detects a first state and a second state, the first and second speaker supports being closed in the first state, the first and second speaker supports being opened and held almost horizontally in the second state, first and second speakers respectively attached on front surfaces of the first and second speaker supports such that a distance in the second state is larger than a distance in the first state, and a reproduction characteristic control unit that switches reproduction characteristics of the first and second speakers in the first state and the second state on the basis of a detection signal from the sensor.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 22, 2022
    Assignee: SONY GROUP CORPORATION
    Inventors: Takayuki Negishi, Jun Komiyama
  • Publication number: 20220068614
    Abstract: The present invention relates to a semiconductor manufacturing member including a silicon carbide-containing boron carbide film at least on a surface thereof, in which the silicon carbide-containing boron carbide film has a content of silicon carbide of 5 wt % or more and 18 wt % or less and a balance being boron carbide.
    Type: Application
    Filed: August 23, 2021
    Publication date: March 3, 2022
    Inventors: Masahiko ICHISHIMA, Hiroshi OISHI, Noriko OMORI, Akira MIYAZAKI, Masahiro KUBOTA, Jun KOMIYAMA
  • Publication number: 20220053252
    Abstract: Provided is an audio reproduction device including: first and second speaker supports that have a lid shape and are provided on a case in an openable and closable manner; a sensor that detects a first state and a second state, the first and second speaker supports being closed in the first state, the first and second speaker supports being opened and held almost horizontally in the second state; first and second speakers respectively attached on front surfaces of the first and second speaker supports such that a distance in the second state is larger than a distance in the first state; and a reproduction characteristic control unit that switches reproduction characteristics of the first and second speakers in the first state and the second state on the basis of a detection signal from the sensor.
    Type: Application
    Filed: November 20, 2019
    Publication date: February 17, 2022
    Inventors: TAKAYUKI NEGISHI, JUN KOMIYAMA
  • Patent number: 11201217
    Abstract: The characteristic of Fe-doped HEMTs is improved. The invention provides a nitride semiconductor substrate having a substrate, a buffer layer made of nitride semiconductors on the substrate, and an active layer composed of nitride semiconductor layers on the buffer layer; the buffer layer containing Fe, the Fe having a concentration profile in which the Fe concentration increases monotonically and gradually in the thickness direction of the buffer layer from an interface between the substrate and the buffer layer, has a maximum value within 2×1017 to 1.1×1020 atoms/cm3 inclusive, and decreases monotonically and gradually toward an interface between the buffer layer and the active layer, and the point of the maximum value being within ±50 nm from the midpoint in the thickness direction of the buffer layer, and being 500 nm or more away from the interface between the buffer layer and the active layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 14, 2021
    Assignee: COORSTEK KK
    Inventors: Kenichi Eriguchi, Yoshihisa Abe, Jun Komiyama
  • Publication number: 20210184004
    Abstract: The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 ?·cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 ?m, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm3 and a specific resistance of 100 to 1000 ?·cm.
    Type: Application
    Filed: November 11, 2020
    Publication date: June 17, 2021
    Applicant: CoorsTek KK
    Inventors: Hiroshi OISHI, Jun KOMIYAMA, Yoshihisa ABE, Kenichi ERIGUCHI
  • Publication number: 20210028284
    Abstract: The characteristic of Fe-doped HEMTs is improved. The invention provides a nitride semiconductor substrate having a substrate, a buffer layer made of nitride semiconductors on the substrate, and an active layer composed of nitride semiconductor layers on the buffer layer; the buffer layer containing Fe, the Fe having a concentration profile in which the Fe concentration increases monotonically and gradually in the thickness direction of the buffer layer from an interface between the substrate and the buffer layer, has a maximum value within 2×1017 to 1.1×1020 atoms/cm3 inclusive, and decreases monotonically and gradually toward an interface between the buffer layer and the active layer, and the point of the maximum value being within ±50 nm from the midpoint in the thickness direction of the buffer layer, and being 500 nm or more away from the interface between the buffer layer and the active layer.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 28, 2021
    Applicant: CoorsTek KK
    Inventors: Kenichi ERIGUCHI, Yoshihisa ABE, Jun KOMIYAMA
  • Patent number: 10825895
    Abstract: A nitride semiconductor substrate can effectively reduce leakage current in the vertical direction. The nitride semiconductor substrate comprises a buffer layer and an operation layer, both of which are made of nitride semiconductor, deposited on a silicon single crystal substrate, wherein the buffer layer comprises a single-layered first initial layer in contact with the silicon single crystal layer, and a single-layered second initial layer in contact with the first initial layer, the first initial layer is made of AlN, the second initial layer is made of AlzGa1-zN (0.12?z?0.65), and in an X-Y graph where the X-axis denotes z×100 and the Y-axis denotes carbon concentration in the second initial layer, X ranges from 12 to 65 and Y is within a range between Y=1E+17×exp(?0.05×X) and Y=1E+21×exp(?0.05×X).
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 3, 2020
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Jun Komiyama
  • Publication number: 20200194545
    Abstract: A nitride semiconductor substrate can effectively reduce leakage current in the vertical direction. The nitride semiconductor substrate comprises a buffer layer and an operation layer, both of which are made of nitride semiconductor, deposited on a silicon single crystal substrate, wherein the buffer layer comprises a single-layered first initial layer in contact with the silicon single crystal layer, and a single-layered second initial layer in contact with the first initial layer, the first initial layer is made of AlN, the second initial layer is made of AlzGa1-zN (0.12?z?0.65), and in an X-Y graph where the X-axis denotes z×100 and the Y-axis denotes carbon concentration in the second initial layer, X ranges from 12 to 65 and Y is within a range between Y=1E+17×exp(?0.05×X) and Y=1E+21×exp(?0.05×X).
    Type: Application
    Filed: October 9, 2019
    Publication date: June 18, 2020
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Jun KOMIYAMA
  • Publication number: 20200194580
    Abstract: Provided is a nitride semiconductor structure capable of preventing deterioration of transistor characteristics caused by diffusion of a P-type conductive element by using an extremely simple configuration, instead of introducing a diffusion suppression layer. A nitride semiconductor substrate comprises at least a layered structure made of group 13 nitride semiconductors, wherein a first layer, a second layer having a wider band gap than the first layer, and a third layer containing a P-type conductive impurity at a concentration of 5E+18 atoms/cc or more are stacked in this order in the layered structure, and a maximum concentration of P-type conductive impurity in the first layer is 10% or less of the concentration of P-type conductive impurity in the third layer.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 18, 2020
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Jun KOMIYAMA
  • Patent number: 10068858
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 4, 2018
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Noriko Omori, Hiroshi Oishi, Jun Komiyama
  • Publication number: 20180151714
    Abstract: Provided is a nitride semiconductor substrate which improves electron mobility and reduce a series resistance component of a transistor. In the nitride semiconductor substrate, an electron transit layer, an intermediate layer, and an electron supply layer are laminated in this order. The electron transit layer includes a nitride semiconductor of a first group 13 element. The intermediate layer and the electron supply layer each include a nitride semiconductor of the first group 13 element and a second group 13 element. The nitride semiconductor substrate has a profile in which an atomic ratio of the second group 13 element to a total of the first group 13 element and the second group 13 element increases in the thickness direction of the intermediate layer from an interface between the electron transit layer and the intermediate layer, and the atomic ratio decreases after a maximum peak value is obtained in the intermediate layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 31, 2018
    Applicant: CoorsTek KK
    Inventors: Noriko OMORI, Hiroshi OISHI, Yoshihisa ABE, Jun KOMIYAMA
  • Patent number: 9748344
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 29, 2017
    Assignee: COORSTEK KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Publication number: 20170110414
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 20, 2017
    Applicant: COORSTEK KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Noriko OMORI, Hiroshi OISHI, Jun KOMIYAMA
  • Publication number: 20170011919
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Applicant: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Patent number: 9536955
    Abstract: A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate 1 is prepared in such a manner that a buffer layer 3 and a semiconductor active layer 4 each comprising a group 13 nitride are stacked one by one on one principal plane of a Si single crystal substrate, the one principal plane has an offset angle of 0.1° to 1° or ?1° to ?0.1° with respect to a (111) plane, an average dopant concentration in a bulk is 1×1018 to 1×1021 cm?3, the Si single crystal substrate 2 has a SiO2 film on the back, and the total thickness of the buffer layer 3 and the semiconductor active layer 4 is 4 to 10 ?m.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 3, 2017
    Assignee: COORSTEK KK
    Inventors: Jun Komiyama, Kenichi Eriguchi, Akira Yoshida, Hiroshi Oishi, Yoshihisa Abe, Shunichi Suzuki
  • Patent number: 9530846
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 27, 2016
    Assignee: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Patent number: D900059
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 27, 2020
    Assignee: SONY CORPORATION
    Inventor: Jun Komiyama
  • Patent number: D928741
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 24, 2021
    Assignee: SONY CORPORATION
    Inventors: Jun Komiyama, Hitoshi Takahashi, Tatsuya Yagihashi, Daisuke Kurihara
  • Patent number: D1008209
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 19, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Jun Komiyama, Kenji Katsumata