Patents by Inventor Jun Kwan Kim
Jun Kwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145268Abstract: A molding apparatus for fabricating a semiconductor package includes an upper mold including an upper cavity, a first side cavity at a first side of the upper cavity, a second side cavity formed at an opposite second side of the upper cavity, and a first driving part connected to the first side cavity and configured to move the first side cavity in a first direction, and a bottom mold including a bottom cavity configured to receive a molding target including a package substrate and at least one semiconductor chip. A width in the first direction between the first side cavity and the second side cavity may be smaller than a width of the package substrate in the first direction and greater than a width in the first direction between a first boundary and a second boundary of the at least one semiconductor chip.Type: ApplicationFiled: September 15, 2023Publication date: May 2, 2024Inventors: Jun Woo Park, Gyu Hyeong Kim, Seung Hwan Kim, Jung Joo Kim, Jong Wan Kim, Yong Kwan Lee
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Patent number: 11955359Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.Type: GrantFiled: March 15, 2021Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Young Oh, Seung Hwan Kim, Jong Ho Park, Yong Kwan Lee, Jong Ho Lee
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Patent number: 11700726Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.Type: GrantFiled: February 2, 2021Date of Patent: July 11, 2023Inventors: Jin Sub Kim, Jun Kwan Kim, Woo Choel Noh, Kyoung-Hee Kim, Ik Soo Kim, Yong Jin Shin
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Publication number: 20230180472Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.Type: ApplicationFiled: January 17, 2023Publication date: June 8, 2023Inventors: Kyoung-Hee KIM, Woo Choel NOH, Ik Soo KIM, Jun Kwan KIM, Jinsub KIM, Yongjin SHIN
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Patent number: 11574871Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: GrantFiled: April 13, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan Kim, Jae-Wha Park, Sang-Hoon Ahn
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Patent number: 11563017Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.Type: GrantFiled: November 17, 2020Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-Hee Kim, Woo Choel Noh, Ik Soo Kim, Jun Kwan Kim, Jinsub Kim, Yongjin Shin
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Patent number: 11557513Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.Type: GrantFiled: March 29, 2021Date of Patent: January 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Keun Kim, Jae Wha Park, Jun Kwan Kim, Hyo Jeong Moon, Seung Jong Park, Seul Gi Bae
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Publication number: 20220344276Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.Type: ApplicationFiled: October 25, 2021Publication date: October 27, 2022Inventors: JINSUB KIM, KYOUNG-HEE KIM, MUNJUN KIM, JUN KWAN KIM, WOO CHOEL NOH
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Publication number: 20210375877Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.Type: ApplicationFiled: February 2, 2021Publication date: December 2, 2021Inventors: Jin Sub KIM, Jun Kwan KIM, Woo Choel NOH, Kyoung-Hee KIM, Ik Soo KIM, Yong Jin SHIN
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Publication number: 20210375896Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.Type: ApplicationFiled: November 17, 2020Publication date: December 2, 2021Inventors: Kyoung-Hee KIM, Woo Choel NOH, Ik Soo KIM, Jun Kwan KIM, Jinsub KIM, Yongjin SHIN
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Publication number: 20210242079Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.Type: ApplicationFiled: March 29, 2021Publication date: August 5, 2021Inventors: Moon Keun KIM, Jae Wha PARK, Jun Kwan KIM, Hyo Jeong MOON, Seung Jong PARK, Seul Gi BAE
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Publication number: 20210233862Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan KIM, Jae-Wha PARK, Sang-Hoon AHN
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Patent number: 11011469Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: GrantFiled: February 26, 2019Date of Patent: May 18, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan Kim, Jae-Wha Park, Sang-Hoon Ahn
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Patent number: 10971395Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.Type: GrantFiled: February 8, 2019Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Keun Kim, Jae Wha Park, Jun Kwan Kim, Hyo Jeong Moon, Seung Jong Park, Seul Gi Bae
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Patent number: 10566284Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.Type: GrantFiled: July 5, 2018Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Kwan Kim, Sanghoon Ahn, Kyu-Hee Han, JaeWha Park, Heesook Park
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Publication number: 20200035613Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.Type: ApplicationFiled: February 26, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-Kwan KIM, Jae-Wha PARK, Sang-Hoon AHN
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Publication number: 20200027783Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.Type: ApplicationFiled: February 8, 2019Publication date: January 23, 2020Inventors: Moon Keun KIM, Jae Wha PARK, Jun Kwan KIM, Hyo Jeong MOON, Seung Jong PARK, Seul Gi BAE
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Publication number: 20190157214Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.Type: ApplicationFiled: July 5, 2018Publication date: May 23, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jun Kwan KIM, Sanghoon AHN, Kyu-Hee HAN, JaeWha PARK, Heesook PARK
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Patent number: 9935194Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.Type: GrantFiled: December 6, 2016Date of Patent: April 3, 2018Assignee: SK Hynix Inc.Inventors: Jin Ha Kim, Jun Kwan Kim, Kang Sik Choi, Su Jin Chae, Young Ho Lee
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Publication number: 20170084740Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Jin Ha KIM, Jun Kwan KIM, Kang Sik CHOI, Su Jin CHAE, Young Ho LEE