Patents by Inventor Jun-Kyu Cho
Jun-Kyu Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11733269Abstract: A semiconductor fabricating apparatus may include a probe card, a test head, a support and a chamber wall. The probe card may include a plurality of probing needles. The probe card may be installed at the test head. The support may be configured to receive a wafer including a plurality of test pads making contact with the probing needles. The chamber wall may be configured to receive the support. The chamber wall may define a chamber in which a probe test may be performed. At least one of the probe card and the support, the probe card and the test head, and the test head and the chamber wall may be combined with each other by a magnetic module.Type: GrantFiled: January 14, 2021Date of Patent: August 22, 2023Assignee: SK hynix Inc.Inventor: Jun-Kyu Cho
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Patent number: 11735452Abstract: An overhead hoist transport system includes a vehicle, a wafer box and a controller. The vehicle includes a combiner. The combiner includes at least one magnetic module. The magnetic module is fixed to a base plate. The magnetic module is downwardly protruded. The wafer box includes a header. The header includes a combining member configured to correspond to the magnetic module. The controller is configured to generate a control signal for controlling attachment and detachment operations between the combiner and the wafer box. The magnetic module includes a frame, a first permanent magnet, a second permanent magnet and a magnetic switch. The frame has an annular cross-sectional shape. The first permanent magnet is fixed to the frame. The second permanent magnet is rotatably arranged in the frame. The magnetic switch is configured to rotate the second magnet in response to the control signal.Type: GrantFiled: October 4, 2021Date of Patent: August 22, 2023Assignee: SK hynix Inc.Inventor: Jun Kyu Cho
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Publication number: 20220108906Abstract: An overhead hoist transport system includes a vehicle, a wafer box and a controller. The vehicle includes a combiner. The combiner includes at least one magnetic module. The magnetic module is fixed to a base plate. The magnetic module is downwardly protruded. The wafer box includes a header. The header includes a combining member configured to correspond to the magnetic module. The controller is configured to generate a control signal for controlling attachment and detachment operations between the combiner and the wafer box. The magnetic module includes a frame, a first permanent magnet, a second permanent magnet and a magnetic switch. The frame has an annular cross-sectional shape. The first permanent magnet is fixed to the frame. The second permanent magnet is rotatably arranged in the frame. The magnetic switch is configured to rotate the second magnet in response to the control signal.Type: ApplicationFiled: October 4, 2021Publication date: April 7, 2022Inventor: Jun Kyu CHO
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Publication number: 20210255219Abstract: A semiconductor fabricating apparatus may include a probe card, a test head, a support and a chamber wall. The probe card may include a plurality of probing needles. The probe card may be installed at the test head. The support may be configured to receive a wafer including a plurality of test pads making contact with the probing needles. The chamber wall may be configured to receive the support. The chamber wall may define a chamber in which a probe test may be performed. At least one of the probe card and the support, the probe card and the test head, and the test head and the chamber wall may be combined with each other by a magnetic module.Type: ApplicationFiled: January 14, 2021Publication date: August 19, 2021Inventor: Jun-Kyu CHO
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Patent number: 7187082Abstract: In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket line extends across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate. The pocket line includes a pocket conductive layer line, a lower metal layer line, and an upper metal layer line, which are sequentially stacked on the pocket insulating later pattern. The device further may further include a line capping layer pattern placed on the pocket line. The line capping layer pattern and the pocket conductive layer line may surround the lower and upper metal layer lines.Type: GrantFiled: September 15, 2004Date of Patent: March 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Kyu Cho, Young-Joon Choi, Byung-Yong Kim
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Patent number: 6960515Abstract: In a method of forming a metal gate electrode, an annealing process is performed in a hydrogen-containing gas ambient following a selective oxidation process. During the annealing process, a metal oxide layer formed by the selective oxidation process is removed by a reduction reaction or hydrogen atoms are contained in the metal oxide layer to suppress whisker nucleation and surface mobility.Type: GrantFiled: December 4, 2001Date of Patent: November 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Mahn-Ho Cho, Ja-Hum Ku, Chul-Joon Choi, Jun-Kyu Cho, Seong-Jun Heo
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Publication number: 20050056935Abstract: In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket line extends across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate. The pocket line includes a pocket conductive layer line, a lower metal layer line, and an upper metal layer line, which are sequentially stacked on the pocket insulating later pattern. The device further may further include a line capping layer pattern placed on the pocket line. The line capping layer pattern and the pocket conductive layer line may surround the lower and upper metal layer lines.Type: ApplicationFiled: September 15, 2004Publication date: March 17, 2005Inventors: Jun-Kyu Cho, Young-Joon Choi, Byung-Yong Kim
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Patent number: 6864132Abstract: Integrated circuit gates are fabricated by forming an insulated gate on an integrated circuit substrate, wherein the insulated gate includes a gate oxide on the integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The insulated gate is pretreated with hydrogen and nitrogen gasses. The polysilicon sidewalls are then oxidized. The pretreating in hydrogen and nitrogen gasses prior to oxidizing can reduce growth in thickness of the gate oxide during the oxidizing and/or can reduce formation of whiskers on the metal pattern, compared to absence of the pretreatment.Type: GrantFiled: February 24, 2003Date of Patent: March 8, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Kyu Cho, Si-Young Choi, Sun-Pil Youn, Sung-Man Kim, Ja-Hum Ku
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Patent number: 6764961Abstract: The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.Type: GrantFiled: November 6, 2001Date of Patent: July 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Mahn-Ho Cho, Chul-Joon Choi, Seong-Jun Heo, Jun-Kyu Cho
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Publication number: 20030224590Abstract: Integrated circuit gates are fabricated by forming an insulated gate on an integrated circuit substrate, wherein the insulated gate includes a gate oxide on the integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The insulated gate is pretreated with hydrogen and nitrogen gasses. The polysilicon sidewalls are then oxidized. The pretreating in hydrogen and nitrogen gasses prior to oxidizing can reduce growth in thickness of the gate oxide during the oxidizing and/or can reduce formation of whiskers on the metal pattern, compared to absence of the pretreatment.Type: ApplicationFiled: February 24, 2003Publication date: December 4, 2003Inventors: Jun-Kyu Cho, Si-Young Choi, Sun-Pil Youn, Sung-Man Kim, Ja-Hum Ku
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Publication number: 20020137321Abstract: The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.Type: ApplicationFiled: November 6, 2001Publication date: September 26, 2002Inventors: Ja-Hum Ku, Mahn-Ho Cho, Chul-Joon Choi, Seong-Jun Heo, Jun-Kyu Cho
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Publication number: 20020127888Abstract: In a method of forming a metal gate electrode, an annealing process is performed in a hydrogen-containing gas ambient following a selective oxidation process. During the annealing process, a metal oxide layer formed by the selective oxidation process is removed by a reduction reaction or hydrogen atoms are contained in the metal oxide layer to suppress whisker nucleation and surface mobility.Type: ApplicationFiled: December 4, 2001Publication date: September 12, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Mahn-Ho Cho, Ja-Hum Ku, Chul-Joon Choi, Jun-Kyu Cho, Seong-Jun Heo