Abstract: Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of (1) searching for devices between which a data transmission path is set up synchronous to different clock signals among the plurality of devices, and (2) adding a plurality of delays only to between the devices having the data transmission path set up therebetween for compensating for the delay coming from a difference of clock signals, whereby solving non-uniformity of clock signals by using a small number of delays.