Patents by Inventor Jun-Lin Tsai
Jun-Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7372102Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.Type: GrantFiled: November 10, 2005Date of Patent: May 13, 2008Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 7250344Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.Type: GrantFiled: November 10, 2005Date of Patent: July 31, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20060063389Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.Type: ApplicationFiled: November 10, 2005Publication date: March 23, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20060063349Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.Type: ApplicationFiled: November 10, 2005Publication date: March 23, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 7015086Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.Type: GrantFiled: February 5, 2004Date of Patent: March 21, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20050176214Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.Type: ApplicationFiled: February 5, 2004Publication date: August 11, 2005Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 6747336Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.Type: GrantFiled: March 13, 2001Date of Patent: June 8, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsing Liu, Chiou-Shian Peng, Kuo-Chio Liu
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Patent number: 6569730Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: March 6, 2002Date of Patent: May 27, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Publication number: 20020105054Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: ApplicationFiled: March 6, 2002Publication date: August 8, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6423590Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: May 2, 2001Date of Patent: July 23, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6396126Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: August 17, 2001Date of Patent: May 28, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jyh-Min Jiang, Jei-Feng Hwang
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Patent number: 6340833Abstract: A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor.Type: GrantFiled: October 23, 2000Date of Patent: January 22, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ruey-Hsin Liu, Jun-Lin Tsai, Yung-Lung Hsu
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Publication number: 20010017379Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: ApplicationFiled: May 2, 2001Publication date: August 30, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
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Publication number: 20010010963Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.Type: ApplicationFiled: March 13, 2001Publication date: August 2, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsing Liu, Chiou-Shian Peng, Kuo-Chio Liu
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Patent number: 6245609Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: GrantFiled: September 27, 1999Date of Patent: June 12, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Patent number: 6242313Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates.Type: GrantFiled: September 3, 1999Date of Patent: June 5, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jei-Feng Hwang, Jun-Lin Tsai, Ruey-Hsin Liou, Jyh-Min Jiang
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Patent number: 6211028Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.Type: GrantFiled: February 5, 1999Date of Patent: April 3, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Ruey-Hsing Liu, Chiou-Shian Peng, Kuo-Chio Liu
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Patent number: 6165861Abstract: A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor.Type: GrantFiled: September 14, 1998Date of Patent: December 26, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ruey-Hsin Liu, Jun-Lin Tsai, Yung-Lung Hsu
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Patent number: 6162695Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.Type: GrantFiled: August 18, 1999Date of Patent: December 19, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jei-Feng Hwang, Jun-Lin Tsai, Ruey-Hsin Liou, Kuo-Chio Liu
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Patent number: 6096629Abstract: A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer.Type: GrantFiled: November 5, 1998Date of Patent: August 1, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jun-Lin Tsai, Yen-Shih Ho