Patents by Inventor Jun-Lin Yeh
Jun-Lin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150058544Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal.Type: ApplicationFiled: October 31, 2014Publication date: February 26, 2015Inventors: Jun-Lin Yeh, Chi-Cheng Lin
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Patent number: 8914569Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.Type: GrantFiled: February 24, 2011Date of Patent: December 16, 2014Assignee: Winbond Electronics Corp.Inventors: Jun-Lin Yeh, Chi-Cheng Lin
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Patent number: 8885383Abstract: A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.Type: GrantFiled: September 26, 2013Date of Patent: November 11, 2014Assignee: Winbond Electronics Corp.Inventors: Jun-Lin Yeh, Ting-Kuo Yen
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Publication number: 20140122813Abstract: A storage medium communicating with a memory controller sent a read command is disclosed. The storage medium includes a plurality of memory units. Each memory unit includes at least sixteen memory cells coupled to a word line and a plurality of bit lines. A controlling unit receives first address information according to the read command and generates a row read signal and a column read signal according to the first address information. A row decoding unit activates the word line according to the row read signal. A column decoding unit activates the bit lines according to the column read signal to output a plurality of storing bits stored in the sixteen memory cells. A read-out unit processes the storing bits to generate a plurality of reading bits. The controlling unit outputs the reading bits to the memory controller in serial.Type: ApplicationFiled: October 29, 2012Publication date: May 1, 2014Applicant: Winbond Electronics Corp.Inventor: Jun-Lin YEH
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Patent number: 8450161Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: May 7, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8404572Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.Type: GrantFiled: February 13, 2009Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Publication number: 20120246384Abstract: A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: WINBOND ELECTRONICS CORP.Inventors: Chi-Cheng Lin, Jun-Lin Yeh
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Publication number: 20120225529Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: May 7, 2012Publication date: September 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Publication number: 20120221766Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.Type: ApplicationFiled: February 24, 2011Publication date: August 30, 2012Applicant: WINBOND ELECTRONICS CORP.Inventors: Jun-Lin Yeh, Chi-Cheng Lin
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Patent number: 8193586Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: February 20, 2009Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
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Publication number: 20100210041Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
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Publication number: 20100044803Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: February 20, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 7203107Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.Type: GrantFiled: December 27, 2005Date of Patent: April 10, 2007Assignee: Winbond Electronics Corp.Inventor: Jun-Lin Yeh
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Publication number: 20060203579Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.Type: ApplicationFiled: December 27, 2005Publication date: September 14, 2006Inventor: Jun-Lin Yeh
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Patent number: 7020003Abstract: A device for compensating a semiconductor memory defect suitable for a semiconductor memory is provided. The device comprises: a memory array, the memory array having a memory region consisting of a plurality of memory cells, the memory array being coupled to the address decoder circuit and the sensing circuit for storing data, if the memory array has a defect, the memory array is divided into a plurality of sub-memory regions, wherein one of the plurality of sub-memory regions is defectless, the memory array is replaced by the defectless sub-memory regions for storing data. A selection circuit coupled to the control unit, selects one of the memory region and the defectless sub-memory region to store data. A first input address buffer coupled to the control unit and the address decoder circuit has an address input port and an address output port.Type: GrantFiled: June 21, 2004Date of Patent: March 28, 2006Assignee: Winbond Electronics Corp.Inventor: Jun-Lin Yeh
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Publication number: 20050174827Abstract: A device for compensating a semiconductor memory defect suitable for a semiconductor memory is provided. The device comprises: a memory array, the memory array having a memory region consisting of a plurality of memory cells, the memory array being coupled to the address decoder circuit and the sensing circuit for storing data, if the memory array has a defect, the memory array is divided into a plurality of sub-memory regions, wherein one of the plurality of sub-memory regions is defectless, the memory array is replaced by the defectless sub-memory regions for storing data. A selection circuit coupled to the control unit, selects one of the memory region and the defectless sub-memory region to store data. A first input address buffer coupled to the control unit and the address decoder circuit has an address input port and an address output port.Type: ApplicationFiled: June 21, 2004Publication date: August 11, 2005Inventor: Jun-Lin Yeh
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Publication number: 20030133328Abstract: A current sense amplifier with dynamic pre-charge is proposed. There is a storage unit having a sense line, a voltage amplifier for generating a first output signal depending on the sense line, a first current mirror for generating a first current depending on the first output signal, a second current mirror for generating a second current depending on a reference storage unit, and a pre-charge circuit for generating a charge up signal on the sense line to pre-charge the sense line to an operation current level depending on the first output signal, the second current and a clock pulse so as to directly detect a data in the storage unit during detecting the sense line.Type: ApplicationFiled: August 8, 2002Publication date: July 17, 2003Applicant: Winbond Electronics Corp.Inventor: Jun-Lin Yeh
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Patent number: 6147529Abstract: A voltage sensing circuit consists of a sensing node, a transistor of a first conductivity type, a diode-like device, a first reference voltage source, a transistor of a second conductivity type, and a second reference voltage source. The transistor of a first conductivity type is configured with one source/drain receiving an input voltage signal and another source/drain connected to the sensing node. The diode-like device receives the input voltage signal and, accordingly, generates a voltage-dropped signal. The first reference voltage source is connected to a gate of the transistor of the first conductivity type. The transistor of a second conductivity type is configured with one source/drain connected to the sensing node and a gate receiving the voltage-dropped signal. The second reference voltage source is connected to another source/drain of the transistor of the second conductivity type.Type: GrantFiled: December 8, 1998Date of Patent: November 14, 2000Assignee: Winbond Electronics Corp.Inventors: Jun-Lin Yeh, Chien-Chung Chen
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Patent number: 5862073Abstract: A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations.Type: GrantFiled: September 15, 1997Date of Patent: January 19, 1999Assignee: Winbond Electronics Corp.Inventors: Jun-Lin Yeh, Ya-Chun Chang