Patents by Inventor Jun Luo
Jun Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260164634Abstract: The present disclosure relates to a vertical channel SRAM cell, a method of manufacturing the same, a memory, and an electronic device, which pertain to a field of semiconductor technology. The vertical channel SRAM cell includes: a pull-up transistor device layer; an intermediate spacer layer on the pull-up transistor device layer; and a pull-down transistor device layer separated from the pull-up transistor device layer by the intermediate spacer layer, where the pull-down transistor device layer includes a pull-down transistor and a pass gate transistor; where the pass gate transistor is connected with the pull-down transistor by an upper source layer at identical height; the first pull-up transistor and the first pull-down transistor form a first inverter, the second pull-up transistor and the second pull-down transistor form a second inverter, and the first inverter and the second inverter are coupled to each other through a metal gate strip.Type: ApplicationFiled: March 19, 2025Publication date: June 11, 2026Inventors: Yongkui ZHANG, Xiaolei WANG, Jun LUO
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Patent number: 12652466Abstract: An optical image stabilization apparatus and a camera module are provided. The optical image stabilization apparatus includes: a shape memory alloy driving component, a fixed component, and a movable component. The shape memory alloy driving component is disposed between the fixed component and the movable component to drive the movable component to move relative to the fixed component. The shape memory alloy driving component is connected with the fixed component and/or the movable component by means of through a metal spacer, and the metal spacer is detabably connected with the fixed component and/or with the movable component.Type: GrantFiled: September 9, 2022Date of Patent: June 9, 2026Assignee: GALAXYCORE SHANGHAI LIMITEDInventors: Wei Tang, Jun Luo
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Publication number: 20260156904Abstract: The present disclosure provides a method of repairing an integrated circuit, which relates to a field of integrated circuit technology. The method of repairing the integrated circuit includes: providing an integrated circuit to be repaired; acquiring a first performance-related parameter and a performance degradation-related parameter of the integrated circuit to be repaired, and establishing a circuit aging model; simulating the integrated circuit to be repaired, and determining the transistor to be repaired in the integrated circuit to be repaired and its first pre-failure duration; acquiring a second performance-related parameter of the transistor to be repaired; determining a repair parameter corresponding to the transistor to be repaired; and repairing the transistor to be repaired according to the first pre-failure duration and the repair parameter by using a gate-induced drain leakage current repair method.Type: ApplicationFiled: July 15, 2025Publication date: June 4, 2026Inventors: Hong YANG, Mingyang SUN, Qianqian LIU, Weihai BU, Xiaolei WANG, Jun LUO, Yongqin WU, Wenwu WANG
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Patent number: 12647704Abstract: Embodiments of this application disclose an optical bus communication method, including: A first terminal obtains first control information from a controller, where the first control information is generated by the controller and is used to control an execution mechanism to work. The first terminal sends the first control information to a central office over a first section, so that the central office forwards the first control information to a second terminal, where the second terminal is connected to the execution mechanism. The first terminal obtains first state information from the central office, where the first state information is used to record a working state of the execution mechanism, the first state information is information sent by the second terminal to the central office over a second section after the second terminal obtains the first control information, and the first section does not overlap with the second section.Type: GrantFiled: August 24, 2023Date of Patent: June 2, 2026Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Lun Zhang, Jun Luo, Su Wang
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Patent number: 12638750Abstract: The present disclosure provides a camera module and a digital device including the camera module. The camera module includes a movable assembly and a fixing assembly. The movable assembly includes a carrier and a first rolling member arranged on a side wall of the carrier, and the first rolling member has a protruding surface protruding from the side wall of the carrier. The fixing assembly includes a base. The base is provided with a first support member, and the first support member is provided with a metal guide rail extending along a direction of an optical axis. When the carrier is installed on the base, the protruding surface of the first rolling member comes into contact with the metal guide rail, and when the movable assembly moves, the first rolling member moves with the movable assembly and forms a rolling or sliding contact with the first support member.Type: GrantFiled: September 14, 2022Date of Patent: May 26, 2026Assignee: GALAXYCORE SHANGHAI LIMITED CORPORATIONInventors: Jun Luo, Yong Xu
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Patent number: 12637648Abstract: A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.Type: GrantFiled: December 5, 2023Date of Patent: May 26, 2026Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Junjie Li, Na Zhou, Enxu Liu, Jianfeng Gao, Junfeng Li, Jun Luo, Wenwu Wang
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Patent number: 12628391Abstract: A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.Type: GrantFiled: December 5, 2023Date of Patent: May 12, 2026Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Junjie Li, Enxu Liu, Na Zhou, Jianfeng Gao, Junfeng Li, Jun Luo, Wenwu Wang
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Patent number: 12623529Abstract: A vehicle driving device includes an electric motor assembly. The electric motor assembly includes: a first electric motor, a second electric motor, and an electric motor controller. An electric motor shaft of the first electric motor and an electric motor shaft of the second electric motor extend in a length direction of a vehicle, and the first electric motor is disposed in front of the second electric motor. The electric motor controller is disposed at a top of the first electric motor and a top of the second electric motor, the first electric motor and the second electric motor are electrically connected to the electric motor controller.Type: GrantFiled: January 21, 2025Date of Patent: May 12, 2026Assignee: BYD Company LimitedInventors: Jiacheng Li, Jun Luo, Dong Zeng
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Publication number: 20260130138Abstract: The present disclosure discloses a method for manufacturing an oxide layer and a semiconductor device, which pertain to the field of semiconductor technology. The method for manufacturing the oxide layer includes: providing a semiconductor structure; forming a first oxide layer on the semiconductor structure in a first low-temperature environment; applying an oxygen plasma treatment on the first oxide layer and a part of the semiconductor structure in a second low-temperature environment, so that the first oxide layer is formed into a second oxide layer, where a compactness of the second oxide layer is greater than a compactness of the first oxide layer. The semiconductor device includes a semiconductor structure and a second oxide layer disposed on the semiconductor structure, where the second oxide layer is manufactured and formed using the aforementioned oxide layer fabrication method.Type: ApplicationFiled: May 20, 2025Publication date: May 7, 2026Inventors: Hong YANG, Songyi JIANG, Junjie LI, Weihai BU, Qianqian LIU, Xiaolei WANG, Jun LUO, Wenwu WANG
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Publication number: 20260129841Abstract: A semiconductor device includes: a substrate; transistors on the substrate, a channel region being between adjacent transistors, the transistor including a surrounding gate layer, a source layer, a drain layer, and a body contact layer, a body contact cavity being between the source layer and the drain layer, and the body contact layer being in the body contact cavity; a bit line at a bottom of the channel region and coupled to the transistor; a word line on a dielectric layer of the channel region and perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line; and a base line in the body contact cavity and the channel region, wherein the base line is in contact with the body contact layer and isolated from the source layer, the drain layer, and the word line, and the base line is parallel to the bit line.Type: ApplicationFiled: December 10, 2024Publication date: May 7, 2026Inventors: Huilong ZHU, Xianyu CHEN, Yongkui ZHANG, Qi WANG, Jun LUO, Tianchun YE
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Publication number: 20260126387Abstract: The present invention discloses an in-situ detection method for reactive oxygen species, which includes the following steps: attaching a reactive oxygen species composite membrane prepared based on a ratiometric fluorescent probe to a to-be-detected region to react with reactive oxygen species; capturing a green light signal on the reactive oxygen species composite membrane using a digital camera equipped with a 520-540 nm narrow-band filter to obtain an image A; capturing a red light signal on the reactive oxygen species composite membrane using a digital camera equipped with a 640-660 nm filter to obtain an image B; acquiring a numerical value (G) of a green light channel in the image A and a numerical value (R) of a red light channel in the image B respectively, and calculating relative fluorescence intensity (FI) as a reactive oxygen species response value; and obtaining a concentration of the reactive oxygen species in situ.Type: ApplicationFiled: December 31, 2025Publication date: May 7, 2026Inventors: Jun LUO, Xing LIU, Longgang CHU, Cheng GU
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Patent number: 12615977Abstract: A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.Type: GrantFiled: December 28, 2023Date of Patent: April 28, 2026Assignees: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Jianfeng Gao, Shuai Yang, Jinbiao Liu, Weibing Liu, Junfeng Li, Jun Luo, Jinjuan Xiang
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Patent number: 12615085Abstract: This application discloses an optical signal control method and apparatus, and belongs to the optical communication field. The apparatus includes: a light source, configured to output a first optical signal; an optical switch module, configured to receive the first optical signal and an external second optical signal, and output a third optical signal; and a detection module, configured to detect whether a power change of the second optical signal on at least one wavelength channel is greater than a preset power change threshold, if so, the optical switch module adjusts on/off states of at least one wavelength channel of the received first optical signal and the at least one wavelength channel of the received second optical signal, so that an adjusted first optical signal and an adjusted second optical signal are combined to obtain the third optical signal.Type: GrantFiled: February 27, 2023Date of Patent: April 28, 2026Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jun Luo, Zhiyong Feng, Jian Zhong
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Publication number: 20260107571Abstract: The semiconductor device includes a base substrate, first and second layer semiconductor structures, first and second contact structures. The second layer semiconductor structure is arranged above the first layer semiconductor structure at intervals along a thickness direction of the base substrate. The first contact structure is arranged in the base substrate and includes a first contact portion in electrical contact with a first source/drain region included in the transistor in the first layer semiconductor structure and a second contact portion in electrical contact with a first gate stack structure. The second contact structure is arranged on a side of the second layer semiconductor structure away from the first layer semiconductor structure and includes a third contact portion in electrical contact with a second source/drain region included in the transistor in the second layer semiconductor structure and a fourth contact portion in electrical contact with a second gate stack structure.Type: ApplicationFiled: July 23, 2025Publication date: April 16, 2026Inventors: Yongliang LI, Huaizhi LUO, Xiaolei WANG, Jun LUO
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Publication number: 20260101570Abstract: The method of manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, where in the thickness direction of the semiconductor substrate, the fin includes first sacrificial layers and channel layers alternately stacked and second sacrificial layers and a third sacrificial layer alternately stacked; forming a mask straddling the fin; selectively removing the second sacrificial layers to form a first dielectric filling region; forming first middle dielectric isolation layers in the first dielectric filling region; removing the first sacrificial layers, the channel layers, the first middle dielectric isolation layers, and the third sacrificial layer not covered by the mask; forming a first source region and a first drain region on both sides of the remaining first sacrificial layers and channel layer located below the remaining first middle dielectric isolation layers, respectively; and forming an insulating layer on the first source region and the first drain region.Type: ApplicationFiled: July 23, 2025Publication date: April 9, 2026Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Yongliang LI, Longyu SUN, Huaizhi LUO, Jun LUO
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Publication number: 20260090069Abstract: The method of manufacturing a semiconductor device includes: forming a fin including first sacrificial layers and channel layers alternately stacked, and second and third sacrificial layers alternately stacked; a material of one of the second and third sacrificial layers including silicon or silicon germanium, and a material of the other one including silicon germanium or germanium; a difference in germanium content between the second and third sacrificial layers being less than 15%, and the second sacrificial layer being doped with an etching auxiliary agent; forming a mask straddling the fin; selectively removing the second sacrificial layers under an accelerated etching effect of the etching auxiliary agent to form a first dielectric filling region; forming first middle dielectric isolation layers in the first dielectric filling region; and removing the first sacrificial layers, the channel layers, the first middle dielectric isolation layers, and the third sacrificial layer not covered by the mask.Type: ApplicationFiled: July 29, 2025Publication date: March 26, 2026Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Yongliang LI, Longyu SUN, Huaizhi LUO, Jun LUO
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Publication number: 20260082692Abstract: Provided is a semiconductor device. The semiconductor device includes: a semiconductor substrate, a first gate-all-around transistor, a second gate-all-around transistor, an insulation layer, and first and second dielectric isolation layers. The insulation layer is arranged between a source/drain region of the first gate-all-around transistor and a source/drain region of the second gate-all-around transistor. The first dielectric isolation layers and the second dielectric isolation layers are alternately stacked between a channel region of the first gate-all-around transistor and a channel region of the second gate-all-around transistor. A gate stack structure of the first gate-all-around transistor and/or a gate stack structure of the second gate-all-around transistor is located at a periphery of alternately stacked first and second dielectric isolation layers.Type: ApplicationFiled: July 17, 2025Publication date: March 19, 2026Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Yongliang LI, Longyu SUN, Huaizhi LUO, Jun LUO
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Publication number: 20260078647Abstract: The present invention relates to the field of drilling coring devices. Disclosed are a pressure-preserved coring tool, a use method, and a reservoir analysis method. The pressure-preserved coring tool comprises an outer cylinder (1), a differential assembly (2), a pressure-preserving inner cylinder assembly (4), and a seal assembly (5). The differential assembly is configured to be able to drive the pressure-pre-serving inner cylinder assembly to move upwards relative to the seal assembly, so that the seal assembly seals the inner cylinder assembly for accommodating a rock core (8).Type: ApplicationFiled: September 8, 2023Publication date: March 19, 2026Inventors: Yang SU, Shaoliang SUN, Ren WANG, Jun LUO, Shangwen ZHOU, Mengyu XIE, Boyi XIA, Xianggang DUAN, Yang JIAO, Liang TANG, Chenchen DONG, Li WEN
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Patent number: 12571898Abstract: Systems and methods for simultaneously recovering and separate sounds from multiple sources using Impulse Radio Ultra-Wideband (IR-UWB) signals are described. In one embodiment, a device can be configured for generating an audio signal based on audio source ranging using ultrawideband signals. In an embodiment the device includes, a transmitter circuitry, a receiver circuitry, memory and a processor. The processor configured to generate a radio signal. The radio signal including an ultra-wideband Gaussian pulse modulated on a radio-frequency carrier. The processor further configured to transmit the radio signal using the transmitter circuitry, receive one or more backscattered signals at the receiver circuitry, demodulate the one or more backscattered signals to generate one or more baseband signals, and generate a set of data frames based on the one or more baseband signals.Type: GrantFiled: November 15, 2022Date of Patent: March 10, 2026Assignees: The Regents of the University of California, Nanyang Technological UniversityInventors: Ziqi Wang, Mani Srivastava, Akash Deep Singh, Luis Garcia, Zhe Chen, Jun Luo
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Patent number: 12565240Abstract: The present disclosure relates to methods and systems for spatiotemporal graph modelling of road users in observed frames of an environment in which an autonomous vehicle operates (i.e. a traffic scene), clustering of the road users into categories, and providing the spatiotemporal graph to a trained graphical convolutional neural network (GNN) to predict a future pedestrian action. The future pedestrian action can be: one of the pedestrian will cross a road and the pedestrian will not cross the road. The spatiotemporal graph includes a better understanding of the observed frames (i.e. traffic scene).Type: GrantFiled: April 28, 2023Date of Patent: March 3, 2026Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Saber Malekmohammadi, Tiffany Yee Kay Yau, Amir Rasouli, Mohsen Rohani, Jun Luo