Abstract: A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

Abstract: A foldable handle includes a base bar, a steering lever pivoted to the base bar, and a movable retaining element. The steering lever has two states relative to the base bar, including a folding state where the steering lever is substantially perpendicular to the base bar and an unfolding state where the steering lever is substantially in the same line with the base bar. The steering lever is configured in a way that in the unfolding state a first side of the steering lever is blocked by a side plate protruded from an end of the base bar to restrict the steering lever to rotate forward. The retaining element is configured to move to be abutted against a second side of the steering lever opposite to the first side blocked by the side plate to restrict the steering lever to rotate backward in the unfolding state of the steering lever.

Abstract: The present invention relates to a kind of pigment preparation, in particular to a modified layered silicate novel barrier and shielding pigment and its preparation method. It is a layer silicate with exchangeable anticorrosive ions as a template, using metal oxides or metal salts, inorganic acids to synthesize nano-spherical zinc phosphate, phosphate, molybdate, borate or tungstate, with rare earth cerium, strontium, lanthanum or praseodymium doped modification of the pigment. The invention uses silicate as a template to effectively control the agglomeration of nanoparticles during the liquid phase deposition process, avoiding the multiple cleaning and sewage treatment processes required by using surfactants and solvents. What is more valuable is lamellar silicic acid. The salt itself has certain anti-corrosion properties and is economical.

Abstract: A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.

Abstract: A method and system for decomposing cross-domain path planning of an amphibious vehicle.

Abstract: Disclosed is an image processing method, electronic device and storage medium. The method includes obtaining feature information of first region in a current image frame, wherein first region includes a region that is determined by performing motion estimation on the current and previous image frames based on optical flow; obtaining feature information of second region in the current image frame, wherein second region includes a region corresponding to pixel points among first pixel points of the current image frame, where its association with pixel points among second pixel points of the previous image frame satisfies a condition; and based on the feature information of first region and that of second region, fusing the previous and current image frames to obtain a processed current image frame, which is used as a previous image frame for a next image frame.

Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; a source, a drain, and at least one nanostructure layer, which are disposed on the semiconductor substrate; and a gate stack structure surrounding each nanostructure layer, where the at least one nanostructure layer is disposed between the source and the drain, each nanostructure layer comprises a first material layer and second material layers, the second material layers are disposed at two sides of the first material layer along a thickness direction of the first material layer, each of the first material layer and the second material layers is in contact with both the source and the drain, and at least a part of the second material layers is different from the first material layer in material.

Abstract: The present disclosure provides an auto focus (AF) method and system for an electro-hydraulic (EH) lens with an adjustable focus, and an electronic device, and relates to the field of lens focusing technologies. The method mainly includes: determining a state space, an action space, and a reward function of a reinforcement learning (RL) method; constructing sample data based on the foregoing determined state space, action space, and reward function, and storing the sample data in an experience pool; and using sample data in the experience pool as training data of a deep neural network (DNN) architecture when there are M sets of the sample data in the experience pool, and obtaining a trained AF policy with reference to a deep deterministic policy gradient (DDPG) algorithm and a single hill climbing optimization (HCO) algorithm.

Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

Abstract: Disclosed is a method for constructing a bionic binocular active visual simultaneous localization and mapping (SLAM) system. The method includes: S1, constructing a binocular active visual system, peripheral vision is simulated using a panoramic camera, a panoramic value map is constructed based on the panoramic camera, and a binocular bionic eye gaze control strategy based on the panoramic value map is proposed; S2, designing a SLAM algorithm framework which is suitable for motion of the two bionic eyes, where relative pose optimization of left and right cameras based on a Perspective-n-Point algorithm and depth calculation for binocular matching points based on triangulation are adopted in a SLAM tracking thread; and S3, with the assistance of camera poses estimated by the SLAM system and sparse landmark point coordinates, training a self-supervised depth estimation network, to provide dense depth estimation for a mapping module of the SLAM system, achieving dense mapping.

Abstract: A method and system for controlling multi-unmanned surface vessel (USV) collaborative search are disclosed which relate to the technical field of the marine intelligent USV collaborative operation. The method includes determining a task region of a USV team; determining environmental perception information corresponding to each of the USVs at the current moment according to the task region and the probability graph mode; inputting the environmental perception information corresponding to each of the USVs at the current moment into the corresponding target search strategy output model respectively to obtain an execution action of each of the USVs at the next moment; sending the execution action of each of the USVs at the next moment to a corresponding USV execution structure to search for underwater targets within the task region. The target search strategy output model is obtained by training based on a training sample and a DDQN network structure.

Abstract: Disclosed is an active positioning method for bionic binocular vision during execution of a simultaneous localization and mapping (SLAM) task. The method includes: capturing a panoramic image using a panoramic camera and detecting key scene information; assigning values to pixels in the panoramic image to obtain a panoramic value map; projecting field-of-view areas of left and right bionic eye cameras separately onto the panoramic value map, to obtain a current binocular field-of-view projection area; calculating a mean value of the current binocular field-of-view projection area in the panoramic value map; comparing the mean value of the current binocular field-of-view projection area with a value threshold, and obtaining a binocular field-of-view projection area with a mean value higher than the value threshold by moving the binocular bionic cameras; and finally using a high-value image captured by the left and right bionic eye cameras as an input of a SLAM system.

Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

Abstract: A cover for HVAC conduits and wiring exiting a structure is provided permitting a simplified solution to protect the line set in an aesthetically pleasing manner. A two-part face plate fits around the conduits and wiring. Each face plate includes a partial cone-shaped protruding member that circumscribes the conduits and wiring once installed. The cover also includes a sleeve that fits around the conduits, distal the cone-shaped protruding members in a tight-fitting manner providing further protection. The cover is easily removeable for a service technician to maintain and repair the conduits or wiring in future servicing.

Abstract: A WLAN system resource indication method and apparatus are provided. The method includes: generating, by an access point, a frame that carries resource indication information; and sending, to multiple stations, the frame that carries the resource indication information. The resource indication information includes multiple pieces of sub resource indication information. Correspondingly, each piece of the sub resource indication information uniquely corresponds to one of the multiple stations. Therefore, a station side does not need read the entire resource indication information, so as to reduce resource overheads and improve efficiency.

Abstract: The disclosure provides proteins specifically binding to Vascular Endothelial Growth Factor (VEGF), transferrin and/or properdin.

Abstract: An apparatus, for determining blood pressure of a subject is provided. The apparatus comprises at least one processor, at least one memory comprising computer program code, and a radio frequency (RF) wave device configured to detect pulse waveform signals from the subject. The at least one memory and the computer program code are configured to, with the at least one processor, determine an estimation of the blood pressure corresponding to the pulse waveform signals using a blood pressure specific transfer function (BTF) derivation model.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.

Abstract: A negative stiffness generating mechanism and a quasi-zero stiffness vibration isolator are provided. A housing is mounted on a base, and the axial relative positions of the housing and the base can be adjusted; a negative stiffness unit comprises inner-ring magnets, outer-ring magnets and a supporting shaft, the supporting shaft axially slides on the base and passes through the housing, the inner-ring magnets fixedly sleeve the supporting shaft, and the outer-ring magnets sleeve outside the inner-ring magnets and are divided into upper and lower groups of outer-ring magnets; the upper and lower groups of outer-ring magnets can synchronously move through a negative stiffness adjusting device; and the axial relative positions of the middle planes of the outer-ring and inner-ring magnets can be adjusted by adjusting the axial relative positions of the housing and the base. The isolator comprises a negative stiffness generating mechanism and a positive stiffness unit.

Abstract: An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.