Abstract: A first detector compares an electric signal to be monitored with a first threshold. A second detector compares the electric signal with a second threshold. A first memory stores setting data of the first threshold. A second memory stores setting data of the second threshold. An interface circuit receives data from an external processor, and writes the data thus received to the first memory and the second memory. The protection circuit is configured such that data writing to the first memory is possible only when a predetermined condition is satisfied.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A control circuit of a digital control power supply circuit includes: an A/D converter that samples a feedback voltage according to an output voltage of the power supply circuit when a strobe signal is asserted, and converts the sampled feedback voltage into digital feedback data; an error detector that generates error data which indicates a difference between the feedback data and target data; a compensator that generates a duty command value which is adjusted to approximate the error data to zero; a digital pulse width modulator that receives the duty command value and generates a pulse signal having a duty ratio corresponding to the duty command value; and a strobe signal generator that generates the strobe signal and adjusts a sampling timing at which the strobe signal is asserted such that the sampling timing approximates a target position set in a substantial center of a slope of the output voltage.

Abstract: An electrical storage device monitoring circuit includes a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the current electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit.

Abstract: An energy harvesting apparatus includes: a capacitor configured to store energy generated by an energy harvesting element; and a switch connected to the capacitor and configured to switch energy supply from the capacitor to a load based on a capacitor voltage with which the capacitor is charged. An energy harvesting system includes: energy harvesting elements; energy harvesting apparatuses which are provided to respectively correspond to the energy harvesting elements; and a load as an energy supply destination connected to the energy harvesting apparatuses.

Abstract: A control circuit of digital control power supply circuit includes: first filter generating detection voltage having voltage level based on time average of output voltage of the digital control power supply circuit; A/D converter sampling feedback voltage having voltage level based on the output voltage at peak or bottom of the output voltage and converting the sampled feedback voltage into digital feedback data, and converting the detection voltage into digital detection data; error detector generating error data indicating difference between the feedback data and target data indicating target value of the feedback voltage; compensator generating duty command value adjusted to make the error data approximate zero; digital pulse modulator receiving the duty command value and generating pulse signal having duty ratio corresponding to the duty command value; and correction unit correcting the target data based on difference between the detection data and the feedback data.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A battery module includes an anode terminal, a cathode terminal, and multiple capacitor cells. Multiple tap electrodes are each provided to a corresponding connection node that connects adjacent capacitor cells. An intermediate terminal is connected to one from among the multiple tap electrodes. A battery control circuit includes a cell balance circuit configured to stabilize each of the voltages at the multiple tap electrodes to a corresponding target voltage level. The voltage at the anode terminal is supplied to the power supply terminal of the cell balance circuit.

Abstract: A first detector compares an electric signal to be monitored with a first threshold. A second detector compares the electric signal with a second threshold. A first memory stores setting data of the first threshold. A second memory stores setting data of the second threshold. An interface circuit receives data from an external processor, and writes the data thus received to the first memory and the second memory. The protection circuit is configured such that data writing to the first memory is possible only when a predetermined condition is satisfied.

Abstract: A power supply circuit is configured including a control circuit together with an output circuit including an external circuit component. A switching controller controls a switching transistor and a synchronous rectification transistor each configured as a switching element. A degradation detection circuit monitors a detection signal having a correlation with characteristic degradation of the circuit component, and detects the degree of characteristic degradation of the circuit component. The switching controller is capable of changing its operation according to the degree of characteristic degradation of the circuit component.

Abstract: A control circuit of digital control power supply circuit includes: first filter generating detection voltage having voltage level based on time average of output voltage of the digital control power supply circuit; A/D converter sampling feedback voltage having voltage level based on the output voltage at peak or bottom of the output voltage and converting the sampled feedback voltage into digital feedback data, and converting the detection voltage into digital detection data; error detector generating error data indicating difference between the feedback data and target data indicating target value of the feedback voltage; compensator generating duty command value adjusted to make the error data approximate zero; digital pulse modulator receiving the duty command value and generating pulse signal having duty ratio corresponding to the duty command value; and correction unit correcting the target data based on difference between the detection data and the feedback data.

Abstract: A control circuit of a digital control power supply circuit includes: an A/D converter that samples a feedback voltage according to an output voltage of the power supply circuit when a strobe signal is asserted, and converts the sampled feedback voltage into digital feedback data; an error detector that generates error data which indicates a difference between the feedback data and target data; a compensator that generates a duty command value which is adjusted to approximate the error data to zero; a digital pulse width modulator that receives the duty command value and generates a pulse signal having a duty ratio corresponding to the duty command value; and a strobe signal generator that generates the strobe signal and adjusts a sampling timing at which the strobe signal is asserted such that the sampling timing approximates a target position set in a substantial center of a slope of the output voltage.

Abstract: An electrical storage device monitoring circuit includes a 3-state buffer configured to switch between a high output state and a low output state based on a flag output delivered from a previous electrical storage device monitoring circuit at a front stage, and also configured to detect a disconnection between the current electrical storage device monitoring circuit and the previous electrical storage device monitoring circuit at the front stage; a detection circuit configured to monitor an electrical storage device to detect whether the electrical storage device is normal or abnormal; and an output circuit configured to deliver the flag output to a subsequent electrical storage device monitoring circuit at a next stage based on an input of the 3-state buffer and a detection result of the detection circuit.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: An energy harvesting apparatus includes: a capacitor configured to store energy generated by an energy harvesting element; and a switch connected to the capacitor and configured to switch energy supply from the capacitor to a load based on a capacitor voltage with which the capacitor is charged. An energy harvesting system includes: energy harvesting elements; energy harvesting apparatuses which are provided to respectively correspond to the energy harvesting elements; and a load as an energy supply destination connected to the energy harvesting apparatuses.

Abstract: A battery module includes an anode terminal, a cathode terminal, and multiple capacitor cells. Multiple tap electrodes are each provided to a corresponding connection node that connects adjacent capacitor cells. An intermediate terminal is connected to one from among the multiple tap electrodes. A battery control circuit includes a cell balance circuit configured to stabilize each of the voltages at the multiple tap electrodes to a corresponding target voltage level. The voltage at the anode terminal is supplied to the power supply terminal of the cell balance circuit.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.