Abstract: A magnetoresistive reproducing head includes first and second free magnetic layers. A non-magnetic layer is provided between the first and second free magnetic layers. A bias applying layer having a single region applies a bias magnetic field in a direction perpendicular to the medium facing plane of the first free-magnetic layer and the second free-magnetic layer. An electrode is electrically connected to the first free-magnetic layer, the second free-magnetic layer, and the non-magnetic layer. In response to a magnetic field generated when a current is applied to the first free-magnetic layer, the second free-magnetic layer, and the non-magnetic layer in a direction perpendicular to the medium facing plane, magnetizations of the first free-magnetic and the second free-magnetic layer are tilted in opposite directions from a direction perpendicular to the medium facing plane.

Abstract: A magnetic read head has a first free-magnetic layer, a second free-magnetic layer, a non-magnetic layer provided between the first free-magnetic layer and the second free-magnetic layer, and a bias applying layer for applying a bias magnetic field in the vertical direction to the medium facing plane of the first free-magnetic layer and the second free-magnetic layer. Shape anisotropies of magnetization of the first free-magnetic layer and the second free-magnetic layer are inclined in the opposite direction with each other for the medium facing plane within film surfaces of respective free-magnetic layers. The first free-magnetic layer and the second free-magnetic layer are overlapped at the medium facing plane in the vertical direction at the surfaces of respective free-magnetic layer films, and the bias applying layer is located on the opposite plane to the medium facing plane of the first free-magnetic layer and the second free-magnetic layer.

Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.