Patents by Inventor Jun Matsuhashi

Jun Matsuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10551432
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20180340976
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Application
    Filed: April 17, 2018
    Publication date: November 29, 2018
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Patent number: 10109568
    Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jun Matsuhashi, Naohiro Makihira, Hidekazu Iwasaki, Toshitsugu Ishii
  • Patent number: 9945903
    Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20180102310
    Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.
    Type: Application
    Filed: August 10, 2017
    Publication date: April 12, 2018
    Inventors: Jun MATSUHASHI, Naohiro MAKIHIRA, Hidekazu IWASAKI, Toshitsugu ISHII
  • Patent number: 9905482
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: February 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20170338159
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 9761501
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20170025318
    Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
    Type: Application
    Filed: May 10, 2016
    Publication date: January 26, 2017
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Patent number: 9515000
    Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20160141215
    Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 19, 2016
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Publication number: 20160064291
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Application
    Filed: April 11, 2013
    Publication date: March 3, 2016
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 8603840
    Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.
    Type: Grant
    Filed: March 11, 2012
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Matsuhashi, Naohiro Makihira
  • Patent number: 8404497
    Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuya Maruyama, Toshikazu Ishikawa, Jun Matsuhashi, Takashi Kikuchi
  • Publication number: 20120244648
    Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.
    Type: Application
    Filed: March 11, 2012
    Publication date: September 27, 2012
    Inventors: Jun MATSUHASHI, Naohiro Makihira
  • Publication number: 20110140105
    Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.
    Type: Application
    Filed: November 15, 2010
    Publication date: June 16, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya MARUYAMA, Toshikazu ISHIKAWA, Jun MATSUHASHI, Takashi KIKUCHI