Patents by Inventor Jun Matsuhashi
Jun Matsuhashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10551432Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.Type: GrantFiled: April 17, 2018Date of Patent: February 4, 2020Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20180340976Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.Type: ApplicationFiled: April 17, 2018Publication date: November 29, 2018Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Patent number: 10109568Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.Type: GrantFiled: August 10, 2017Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Jun Matsuhashi, Naohiro Makihira, Hidekazu Iwasaki, Toshitsugu Ishii
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Patent number: 9945903Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.Type: GrantFiled: May 10, 2016Date of Patent: April 17, 2018Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20180102310Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.Type: ApplicationFiled: August 10, 2017Publication date: April 12, 2018Inventors: Jun MATSUHASHI, Naohiro MAKIHIRA, Hidekazu IWASAKI, Toshitsugu ISHII
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Patent number: 9905482Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: GrantFiled: August 9, 2017Date of Patent: February 27, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20170338159Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: ApplicationFiled: August 9, 2017Publication date: November 23, 2017Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Patent number: 9761501Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: GrantFiled: April 11, 2013Date of Patent: September 12, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20170025318Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.Type: ApplicationFiled: May 10, 2016Publication date: January 26, 2017Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Patent number: 9515000Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.Type: GrantFiled: October 30, 2015Date of Patent: December 6, 2016Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20160141215Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.Type: ApplicationFiled: October 30, 2015Publication date: May 19, 2016Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Publication number: 20160064291Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: ApplicationFiled: April 11, 2013Publication date: March 3, 2016Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Patent number: 8603840Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.Type: GrantFiled: March 11, 2012Date of Patent: December 10, 2013Assignee: Renesas Electronics CorporationInventors: Jun Matsuhashi, Naohiro Makihira
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Patent number: 8404497Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.Type: GrantFiled: November 15, 2010Date of Patent: March 26, 2013Assignee: Renesas Electronics CorporationInventors: Kazuya Maruyama, Toshikazu Ishikawa, Jun Matsuhashi, Takashi Kikuchi
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Publication number: 20120244648Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.Type: ApplicationFiled: March 11, 2012Publication date: September 27, 2012Inventors: Jun MATSUHASHI, Naohiro Makihira
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Publication number: 20110140105Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.Type: ApplicationFiled: November 15, 2010Publication date: June 16, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kazuya MARUYAMA, Toshikazu ISHIKAWA, Jun MATSUHASHI, Takashi KIKUCHI