Patents by Inventor Jun Morioka

Jun Morioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9337331
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kanako Komatsu, Mariko Shimizu, Jun Morioka, Keita Takahashi, Masahito Nishigoori
  • Publication number: 20150357464
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kanako KOMATSU, Mariko SHIMIZU, Jun MORIOKA, Keita TAKAHASHI, Masahito NISHIGOORI
  • Patent number: 9142613
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kanako Komatsu, Mariko Shimizu, Jun Morioka, Keita Takahashi, Masahito Nishigoori
  • Publication number: 20140339635
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 20, 2014
    Inventors: Kanako KOMATSU, Mariko SHIMIZU, Jun MORIOKA, Keita TAKAHASHI, Masahito NISHIGOORI
  • Patent number: 8836025
    Abstract: According to one embodiment, a first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between an edge of the second insulating film on an inner peripheral side of the second semiconductor layer and an edge of the third semiconductor layer on an outer peripheral side of the second semiconductor layer. The second distance in the first region is shorter than the second distance in the second region.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Shimizu, Jun Morioka, Keita Takahashi, Kanako Komatsu, Masahito Nishigoori
  • Publication number: 20140054693
    Abstract: According to one embodiment, a first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between an edge of the second insulating film on an inner peripheral side of the second semiconductor layer and an edge of the third semiconductor layer on an outer peripheral side of the second semiconductor layer. The second distance in the first region is shorter than the second distance in the second region.
    Type: Application
    Filed: February 11, 2013
    Publication date: February 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mariko SHIMIZU, Jun MORIOKA, Keita TAKAHASHI, Kanako KOMATSU, Masahito NISHIGOORI
  • Publication number: 20130270637
    Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.
    Type: Application
    Filed: March 25, 2013
    Publication date: October 17, 2013
    Inventors: Kanako KOMATSU, Jun Morioka, Koji Shirai, Keita Takahashi, Tsubasa Yamada, Mariko Shimizu
  • Patent number: 8421153
    Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Jun Morioka, Koji Shirai, Keita Takahashi, Tsubasa Yamada, Mariko Shimizu
  • Patent number: 8304827
    Abstract: A semiconductor device includes a diode formed by making use of a DMOS transistor structure. In addition to such a DMOS transistor structure, the semiconductor device includes a second buried layer of the first conductivity type being provided on a first buried layer of a second conductivity type that is in a floating state. Moreover, the second buried layer of the first conductivity type and a second diffusion region of the first conductive type are connected by a first diffusion region of the first conductivity type. A first electrode is set as anode, and a second electrode and a third electrode are short-circuited and set as cathode.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Nakamura, Koji Shirai, Hirofumi Nagano, Jun Morioka, Tsubasa Yamada, Kazuaki Yamaura, Yasunori Iwatsu
  • Patent number: 8299548
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Tsubasa Yamada, Jun Morioka, Koji Kimura
  • Publication number: 20120241858
    Abstract: A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.
    Type: Application
    Filed: September 22, 2011
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Jun Morioka, Koji Shirai, Keita Takahashi, Tsubasa Yamada, Mariko Shimizu
  • Publication number: 20120187485
    Abstract: According to an embodiment of the invention, a semiconductor device includes a substrate, a second conductive type source region formed in the substrate, a second conductive type drain region formed in the substrate, a first conductive type channel region formed in the substrate, a second conductive type drift region formed between the first conductive type channel region and the second conductive type drain region, an insulator film buried on a surface of the second conductive type drift region, and a gate electrode including an opening between the first conductive type channel region and the insulator film and covering a surface of the substrate from the first conductive type channel region to part of the insulator film via a gate insulator. The second conductive type drift region includes a second portion of the second conductive type drift region formed in the substrate below the opening.
    Type: Application
    Filed: August 5, 2011
    Publication date: July 26, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Jun MORIOKA
  • Publication number: 20120025307
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include simultaneously forming a first field insulating film and at least one second field insulating film on a front face side of a semiconductor layer. The at least one second field insulating film is separated from the first field insulating film and thinner than the first field insulating film. The method can include forming a drift region of a first conductivity type in a region of the semiconductor layer including the first field insulating film and the second field insulating film. The method can include forming a drain region of the first conductivity type in the front face of the semiconductor layer on a side of the first field insulating film. In addition, the method can include forming a source region of the first conductivity type in the front face of the semiconductor layer on a side of the second field insulating film.
    Type: Application
    Filed: March 17, 2011
    Publication date: February 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kanako Komatsu, Tsubasa Yamada, Jun Morioka, Koji Kimura
  • Publication number: 20100163973
    Abstract: A semiconductor device includes a P-type substrate 1, an N-type buried layer 2, a P-type buried layer 3, N-type epitaxial layers 4, P-type diffusion layers 6, P-type diffusion layers 8, P-type diffusion layers 11, first electrodes formed on the P-type diffusion layers 11, N-type diffusion layers 9, P-type diffusion layers 12, N-type diffusion layers 13, second electrodes formed on the P-type diffusion layers 12 and the N-type diffusion layers 13, and gate electrodes 10 short-circuited with the second electrodes. The N-type buried layer 2 is in a floating state.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki Nakamura, Koji Shirai, Hirofumi Nagano, Jun Morioka, Tsubasa Yamada, Kazuaki Yamaura, Yasunori Iwatsu
  • Publication number: 20080029809
    Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer on a major surface thereof. The semiconductor layer is formed to extend in the vertical direction of the major surface of the semiconductor substrate. A stress application layer is provided on either side of the semiconductor layer and applies a stress to the semiconductor layer.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 7, 2008
    Inventors: Jun Morioka, Shinichi Taka, Kiminori Watanabe, Koji Yonemura, Chihiro Yoshino, Keita Takahashi