Abstract: In a monitor circuit, a data signal is propagated from an FF to another FF via a data delay circuit. The data delay circuit selects any one from among data paths that delay the data signal in accordance with a selection signal. A clock signal that is input to the FF is input to the other FF via a clock delay circuit. The clock delay circuit selects any one from among clock paths that delay the clock signal in accordance with another selection signal.

Abstract: In a monitor circuit, a data signal is propagated from an FF to another FF via a data delay circuit. The data delay circuit selects any one from among data paths that delay the data signal in accordance with a selection signal. A clock signal that is input to the FF is input to the other FF via a clock delay circuit. The clock delay circuit selects any one from among clock paths that delay the clock signal in accordance with another selection signal.

Abstract: An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.

Abstract: A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.

Abstract: An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.

Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Abstract: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Abstract: A semiconductor device includes a memory element including a stack structure stacking an insulator film and a metal film or a metal compound film; and a transistor including a gate structure having an identical stack structure as that of the memory element.

Abstract: A silicide region includes a first contact region, a fuse region having a narrower longitudinal width than that of the first contact region, and a second contact region provided on an opposite side of the fuse region with respect to the first contact region. A non-silicide region is provided at a position adjacent to a non-fuse-contacting side that is opposite to a side on which the second contact region in contact with the fuse region.

Abstract: The fuse comprises an interconnection part 14 luding a silicon layer; a contact part 20b connected one end of the interconnection part 14; and a contact part 20aconnected to the other end of the interconnection part 14 and containing a metal material. A current is flowed from the contact part 20bto the contact part 20a to migrate the metal material of the contact part 20a to the silicon layer to thereby change the contact resistance between the interconnection part 14 and the contact part 20a.