Patents by Inventor Jun Nakamoto

Jun Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7019076
    Abstract: The invention provides a rubber-modified copolymer resin which is excellent in transparency, impact resistance and rigidity and which has little dependency of the transparency on molding conditions, and a rubber-modified copolymer resin composition which has the above characteristics and which has high practical strength. A transparent rubber-modified copolymer resin which is a rubber-modified copolymer resin obtained by copolymerizing a styrenic monomer and a (meth)acrylic ester monomer in the presence of a rubbery polymer, and which is characterized in that the volume mean particle diameter of rubber particles dispersed in the resin, is from 0.4 to 2.0 ?m, and in the cumulative rubber particle size distribution curve by volume, the difference between the diameter at an integrated value of 75% and the diameter at an integrated value of 25%, is from 0.2 to 2.0 ?m; and a rubber-modified copolymer resin composition comprising from 60 to 99.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: March 28, 2006
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Jun Takahashi, Jun Nakamoto, Hideki Watanabe
  • Publication number: 20040249073
    Abstract: The invention provides a rubber-modified copolymer resin which is excellent in transparency, impact resistance and rigidity and which has little dependency of the transparency on molding conditions, and a rubber-modified copolymer resin composition which has the above characteristics and which has high practical strength.
    Type: Application
    Filed: April 12, 2004
    Publication date: December 9, 2004
    Inventors: Jun Takahashi, Jun Nakamoto, Hideki Watanabe
  • Patent number: 5109360
    Abstract: A memory system in which access to faulty memory blocks is prevented. A test is carried out to see if there are enough functional memory blocks to store a given amount of information. If not, an address mode signal is generated that interchanges the row/column accesses for a given multi-bit address word, such that a line fault is isolated to only one memory block. This reconfigures the system to maximize available memory space without adding excessive access delays.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: April 28, 1992
    Assignee: International Business Machines Corporation
    Inventors: Junichi Inazumi, Shigetaka Inazumi, Jun Nakamoto