Patents by Inventor Jun-noh Lee
Jun-noh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299182Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventor: JUN NOH LEE
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Patent number: 11699743Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.Type: GrantFiled: September 29, 2021Date of Patent: July 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Jun Noh Lee
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Publication number: 20220020866Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventor: JUN NOH LEE
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Patent number: 11139387Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.Type: GrantFiled: August 23, 2019Date of Patent: October 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Jun Noh Lee
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Patent number: 10748909Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: GrantFiled: December 12, 2019Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Publication number: 20200127126Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.Type: ApplicationFiled: August 23, 2019Publication date: April 23, 2020Inventor: JUN NOH LEE
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Publication number: 20200119021Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon MA, Jun-Noh Lee, Dong-Hyun IM, Youngseok Kim, Kongsoo Lee
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Patent number: 10535663Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: GrantFiled: January 11, 2019Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Publication number: 20190148383Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: ApplicationFiled: January 11, 2019Publication date: May 16, 2019Inventors: Jinwon MA, JUN-NOH LEE, DONG-HYUN IM, YOUNGSEOK KIM, KONGSOO LEE
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Patent number: 10211210Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: GrantFiled: May 24, 2017Date of Patent: February 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Patent number: 10008505Abstract: A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.Type: GrantFiled: June 30, 2016Date of Patent: June 26, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Noh Lee, Youngkuk Kim, Sangyeol Kang, Joonsoo Park, KiVin Im
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Publication number: 20170345824Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: ApplicationFiled: May 24, 2017Publication date: November 30, 2017Inventors: Jinwon MA, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Patent number: 9666433Abstract: Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.Type: GrantFiled: April 15, 2016Date of Patent: May 30, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Badro Im, Yoonchul Cho, Sangyeol Kang, Daehyun Kim, Dongkak Lee, Jun-Noh Lee, Bonghyun Kim, Kongsoo Lee
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Publication number: 20170018553Abstract: A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.Type: ApplicationFiled: June 30, 2016Publication date: January 19, 2017Inventors: Jun-Noh LEE, YOUNGKUK KIM, SANGYEOL KANG, JOONSOO PARK, KiVin IM
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Publication number: 20160351408Abstract: Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.Type: ApplicationFiled: April 15, 2016Publication date: December 1, 2016Inventors: BADRO IM, YOONCHUL CHO, SANGYEOL KANG, DAEHYUN KIM, DONGKAK LEE, JUN-NOH LEE, BONGHYUN KIM, KONGSOO LEE
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Publication number: 20140367774Abstract: Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Inventors: Jong-Ryeol Yoo, Jun-Noh Lee, Dong-Chan Kim, Han-Jin Lim
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Patent number: 8710564Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: GrantFiled: March 13, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Patent number: 8698221Abstract: A capacitor includes a first electrode, a first dielectric layer disposed on the first electrode, the first dielectric layer having a tetragonal crystal structure and including a first metal oxide layer doped with a first impurity, a second dielectric layer disposed on the first metal oxide layer, the second dielectric layer having a tetragonal crystal structure and including a second metal oxide layer doped with a second impurity, and a second electrode disposed on the second dielectric layer. The first dielectric layer has a lower crystallization temperature and a substantially higher dielectric constant than the second dielectric layer.Type: GrantFiled: November 7, 2011Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kiyeon Park, Insang Jeon, Hanjin Lim, Yeongcheol Lee, Jun-Noh Lee
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Patent number: 8361551Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.Type: GrantFiled: December 29, 2009Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Ki-Yeon Park, Jun-Noh Lee
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Publication number: 20120168904Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang