Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.

Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown in an electrode formation process when an electrode and an amplifier are provided on a same substrate. A diode is provided of which a cathode is connected to a previous stage of an amplifying transistor for amplifying a signal read by a read electrode for reading a potential having contact with liquid in which a specimen is input and an anode is grounded. With such a configuration, by bypassing a negative charge generated between the electrode and the amplifying transistor in the electrode formation process from the diode and discharging the negative charge toward ground so as to prevent electrostatic breakdown. This is applicable to a bioelectric potential measuring apparatus.

Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.

Abstract: There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.

Abstract: There is provided a semiconductor device including: a plurality of bumps (13) on a first semiconductor substrate (11); and a lens material (57) in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.

Abstract: A potential measurement device according to the present disclosure includes a plurality of read-out electrodes arranged in an array shape and configured to detect a potential at a potential generation point generated due to a chemical change, and a reference electrode configured to detect a reference potential. The reference electrode is arranged within the array of the read-out electrodes. With this configuration, a low-noise potential measurement device in which noise superimposed on a wire from each of the read-out electrodes to an amplifier and noise superimposed on a wire from the reference electrode to the amplifier, i.e., wiring noise, can be reduced is achieved.

Abstract: The present technology relates to a solid-state imaging device, an imaging apparatus, an electronic apparatus, and a semiconductor device, which can prevent overflow of an underfilling resin filled in a portion adapted to connect the substrate to the flip chip and can prevent secondary damages such as electric short-circuit and contact with processing equipment. By utilizing a molding technology of forming an on-chip lens, a dam is formed in a ring shape or a square shape in a manner surrounding a range where a flip chip is connected via a solder bump on an upper layer of a substrate of the solid-state imaging device and provided in order to form the on-chip lens. This can block the underfilling resin filled in the range where the substrate and the flip chip are electrically connected. The present technology can be applied to a solid-state imaging device.

Abstract: There is provided a semiconductor device including: a plurality of bumps (13) on a first semiconductor substrate (11); and a lens material (57) in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.

Abstract: The present technology relates to a solid-state imaging device, an imaging apparatus, an electronic apparatus, and a semiconductor device, which can prevent overflow of an underfilling resin filled in a portion adapted to connect the substrate to the flip chip and can prevent secondary damages such as electric short-circuit and contact with processing equipment. By utilizing a molding technology of forming an on-chip lens, a dam is formed in a ring shape or a square shape in a manner surrounding a range where a flip chip is connected via a solder bump on an upper layer of a substrate of the solid-state imaging device and provided in order to form the on-chip lens. This can block the underfilling resin filled in the range where the substrate and the flip chip are electrically connected. The present technology can be applied to a solid-state imaging device.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cells and a control circuit. The memory cell includes a semiconductor layer, a gate insulating layer, a floating gate, a lower control gate, and an upper control gate. The semiconductor layer extends in a certain direction. The lower control gate is formed on the floating gate via an insulating layer. The upper control gate is formed on the lower control gate via an insulating layer. In addition, the control circuit, when performing a write operation, applies a first pass voltage to the upper control gate in a selected memory cell, and applies a first write voltage which is larger than the first pass voltage to the upper control gate in an adjacent memory cell formed on an identical semiconductor layer to the selected memory cell and adjacent to the selected memory cell.

Abstract: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other.

Abstract: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.