Abstract: A potential of −3V is applied to a control gate electrode, a potential of 5V is applied to a pair of impurity regions and a potential of 3V is applied to a semiconductor substrate in a non-volatile semiconductor memory device. Accordingly, electrons existing on one impurity region side in a silicon nitride film move toward that impurity region, and electrons existing on the other impurity region side move toward that impurity region. Furthermore, electrons existing in that part (middle part) of the silicon nitride film which is positioned immediately above a region approximately at the middle point between one impurity region and the other impurity region move toward the semiconductor substrate. Therefore, MPE (Miss Placed Electron) is no longer caused in the non-volatile semiconductor memory device.

Abstract: At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

Abstract: When a non-volatile memory cell which can store two bits per one memory cell and pass current bidirectionally is used, a bias power source potential is provided also to a bit line BL4 adjacent to two bit lines (BL2 and BL2) passing a sense current BL2 and BL3. Switch units are provided corresponding to each bit line for selectively connect to any one of a ground power source line, read power source line or bias power source line. The current flowing from a sense amplifier circuit to the adjacent bit line BL4 via adjacent memory cell can be reduced, and thus the current in the sense amplifier circuit is stabilized quickly. Accordingly, a non-volatile semiconductor memory device allows high-speed data reading operation.

Abstract: A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.

Abstract: A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.

Abstract: A non-volatile semiconductor memory device of the present invention is provided with a semiconductor substrate having a main surface, an ONO film (a laminated film of an oxide film, a nitride film and an oxide film) formed on the main surface and having a charge storage part, a pair of buried diffusion bit lines formed in the semiconductor substrate located on both sides of the ONO film, oxide films deposited on the main surface so as to cover the buried diffusion bit lines, and a transfer gate electrode formed on the ONO film.

Abstract: Each of program units which is arranged to be adjacent to a memory array, stores redundant information of 1 bit necessary for replacement and repair. Prior to normal data read operation, the redundant information read from the program units is latched in a row select circuit. The row select circuit selectively activates one of word lines corresponding to the normal memory cells and a spare word line in accordance with whether the defective row addresses indicated by the redundant information are matched to an inputted row addresses, respectively.

Abstract: In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

Abstract: A first selector circuit selectively outputs eight of a plurality of data read from a regular memory cell array, to correspond to the number of data output for one read operation in a testing operation. A second selector circuit selectively outputs eight of a plurality of data read from a spare memory cell array. A third selector circuit in a test mode of operation receives an output of the first selector circuit and that of the second selector circuit and when the operation test of interest is to be conducted for a spare memory cell the third selector circuit outputs to a tester apparatus the output of the second selector circuit as testing output data TDout.

Abstract: Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.

Abstract: A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.

Abstract: Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.

Abstract: A first selector circuit selectively outputs eight of a plurality of data read from a regular memory cell array, to correspond to the number of data output for one read operation in a testing operation. A second selector circuit selectively outputs eight of a plurality of data read from a spare memory cell array. A third selector circuit in a test mode of operation receives an output of the first selector circuit and that of the second selector circuit and when the operation test of interest is to be conducted for a spare memory cell the third selector circuit outputs to a tester apparatus the output of the second selector circuit as testing output data TDout.

Abstract: Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

Abstract: In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.

Abstract: A first memory of a large storage capacity is connected to a DQ pad for inputting and outputting an information signal through a bus interface unit. A first bidirectional transfer circuit and a second bidirectional transfer circuit for bidirectionally transmitting an information signal are provided between a high-speed memory and the memory of the large storage capacity. The first bidirectional transfer circuit is connected with the large storage capacity memory through a common bus, and the high-speed memory is interconnected with the second transfer circuit through a fifth bus. This second bidirectional transfer circuit is connected to an instruction register and a data register through a sixth bus. A processor is arranged in proximity to this instruction register and the data register, so that the processor processes an instruction from the instruction register and data from the data register and stores a processing result in the data register again.

Abstract: Registers are arranged along at least opposite two sides of the four sides of a dynamic random access memory cell array. The registers are interconnected via an internal data bus line used for internal data transfer for the memory cell array. At least one register of the registers arranged along the opposite two sides is coupled with an external data bus, and the other register is coupled with an internal circuit via an internal data bus. An external controller which controls an operation in response to an external control signal is provided for the register coupled with an external circuit. An internal controller which controls an operation according to a control signal from the internal circuit is provided for the register coupled with the internal circuit. The external and internal circuits are permitted to simultaneously access the memory cell array only when the external and internal circuits read the data of a memory cell located at the same address of the memory cell array.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

Abstract: A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.