Abstract: A scheduling apparatus includes a state information acquisition unit that acquires, from a decoding unit, state information that serves as an indicator for computing a processing time actually required for a decoding unit to perform a decoding process on first processing target data, and a schedule generating unit that determines a second scheduled processing time for which the decoding unit is able to perform the decoding process on second processing target data, based on the processing time computed based on the state information. The schedule generating unit further generates a second schedule for the decoding unit to perform the decoding process on the second processing target data, by allocating the second scheduled processing time to the decoding unit.

Abstract: A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's individual control bus and a common control bus. A bus selector is disposed between the individual control buses and the common control bus and controlled by a bus arbiter that resolves bus requests on the individual control buses from the processors attempting access to the data memory. The bus arbiter sends a selection command to the bus selector, thereby permitting a specified processor to reach the data memory. A bus monitor counts bus requests and conflicts between them, determines priority of each processor attempting access to the data memory according to the count results, and sends a wait command signal to low-priority processors so as to delay their access to the data memory.

Abstract: A scheduling apparatus includes a state information acquisition unit that acquires, from a decoding unit, state information that serves as an indicator for computing a processing time actually required for a decoding unit to perform a decoding process on first processing target data, and a schedule generating unit that determines a second scheduled processing time for which the decoding unit is able to perform the decoding process on second processing target data, based on the processing time computed based on the state information. The schedule generating unit further generates a second schedule for the decoding unit to perform the decoding process on the second processing target data, by allocating the second scheduled processing time to the decoding unit.

Abstract: A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's individual control bus and a common control bus. A bus selector is disposed between the individual control buses and the common control bus and controlled by a bus arbiter that resolves bus requests on the individual control buses from the processors attempting access to the data memory. The bus arbiter sends a selection command to the bus selector, thereby permitting a specified processor to reach the data memory. A bus monitor counts bus requests and conflicts between them, determines priority of each processor attempting access to the data memory according to the count results, and sends a wait command signal to low-priority processors so as to delay their access to the data memory.

Abstract: A receiving circuit, which prevents spikes included in reproduced clock signals, caused by a time slot change in the division multiplex wireless communication or by the switching of diversity antenna, from being transmitted to the following circuits, and thereby eliminates errors in the determination of the received data, has a demodulator coupled to an antenna for demodulating signals received therefrom, a selector coupled to the demodulator for selecting from a plurality of clock signals reproduced from the data of the respective time slots, one of the reproduced clock signals. A time division timing control circuit is coupled to the selector and to a switching circuit, which control circuit is supplied with an internal clock signal from an internal clock generation circuit. The switching circuit is coupled to the output terminal of the selector and selects and outputs either the internal clock signal or the selected reproduced clock signal.