Patents by Inventor Jun Rye Rho

Jun Rye Rho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210191636
    Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on completion pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.
    Type: Application
    Filed: July 1, 2020
    Publication date: June 24, 2021
    Inventors: Seung Gu JI, Jun Rye RHO
  • Patent number: 9825651
    Abstract: An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jun-Rye Rho, Sung-Gun Cho
  • Publication number: 20170017417
    Abstract: A data storage device includes a nonvolatile memory apparatus including a page including a plurality of chunk areas respectively corresponding to a plurality of data chunks; and a controller including a memory, and suitable for generating parity data by independently encoding one of the plural data chunk, storing the data chunk in one of the plural chunk areas of the page and storing the parity data in the memory as intermediate parity data.
    Type: Application
    Filed: December 2, 2015
    Publication date: January 19, 2017
    Inventors: Chol Su CHAE, Jun Rye RHO
  • Publication number: 20160378595
    Abstract: An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.
    Type: Application
    Filed: December 3, 2015
    Publication date: December 29, 2016
    Inventors: Jun-Rye RHO, Sung-Gun CHO
  • Patent number: 9513991
    Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jun Rye Rho
  • Patent number: 9378134
    Abstract: Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device. A non-volatile memory system may include a memory controller suitable for controlling a memory; and the memory suitable for performing read and program operations in response to commands from the memory controller, and wherein the memory controller and the memory operate in a high interface mode, and operate in a low interface mode when an operation to read internal data or an operation to receive (N+1)th data is performed during an operation to program Nth data in the memory.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Inc.
    Inventors: Byoung-Sung Yoo, Eui-Jin Kim, Jun-Rye Rho
  • Patent number: 9367388
    Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jun Rye Rho
  • Patent number: 9171611
    Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 27, 2015
    Assignee: SK HYNIX INC.
    Inventor: Jun Rye Rho
  • Publication number: 20150235697
    Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.
    Type: Application
    Filed: June 20, 2014
    Publication date: August 20, 2015
    Inventor: Jun Rye RHO
  • Publication number: 20150154067
    Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.
    Type: Application
    Filed: May 13, 2014
    Publication date: June 4, 2015
    Applicant: SK hynix Inc.
    Inventor: Jun Rye RHO
  • Patent number: 8953375
    Abstract: A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jun-Rye Rho, Seok-Hwan Choi
  • Publication number: 20140359204
    Abstract: Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device. A non-volatile memory system may include a memory controller suitable for controlling a memory; and the memory suitable for performing read and program operations in response to commands from the memory controller, and wherein the memory controller and the memory operate in a high interface mode, and operate in a low interface mode when an operation to read internal data or an operation to receive (N+1)th data is performed during an operation to program Nth data in the memory.
    Type: Application
    Filed: December 11, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventors: Byoung-Sung YOO, Eui-Jin KIM, Jun-Rye RHO
  • Publication number: 20140208187
    Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.
    Type: Application
    Filed: March 16, 2013
    Publication date: July 24, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jun Rye RHO
  • Patent number: 8713407
    Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Rye Rho
  • Patent number: 8593864
    Abstract: A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit line in response to a voltage level corresponding to a value of program data.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: November 26, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Rye Rho
  • Publication number: 20130170295
    Abstract: A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.
    Type: Application
    Filed: August 22, 2012
    Publication date: July 4, 2013
    Inventors: Jun-Rye RHO, Seok-Hwan CHOI
  • Publication number: 20120320676
    Abstract: A semiconductor system includes a host configured to output a command, a control signal, an address signal, and data; and a nonvolatile memory apparatus configured to receive at least one of the command, the control signal, the address signal, and the data from the host, to provide a process result to the host, and to determine data levels of memory cells included in an overlap section of memory cell threshold voltage distributions based on an initial read bias voltage.
    Type: Application
    Filed: December 27, 2011
    Publication date: December 20, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sang Chul LEE, Jun Rye RHO, Sang Sik KIM
  • Publication number: 20120269003
    Abstract: A data decision method including checking whether threshold voltages of a plurality of memory cells are greater than a first verification voltage, checking whether the threshold voltages of the plurality of memory cells are greater than a second verification voltage, wherein the second verification voltage is greater than the first verification voltage, and checking threshold voltages of memory cells adjacent to memory cells having threshold voltages greater than the first verification voltage and lower than the second verification voltage among the plurality of memory cells.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 25, 2012
    Inventors: Sang-Sik KIM, Jun-Rye RHO, Sang-Chul LEE
  • Patent number: 8286055
    Abstract: A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 9, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun Rye Rho
  • Publication number: 20120185654
    Abstract: A semiconductor apparatus includes a plurality of linear feedback shift registers configured to receive a plurality of seed codes as initial values and generate respective random codes under a control of a clock signal, a code combination section configured to logically combine the plurality of random codes generated by the plurality of linear feedback shift registers and generate a final random code, and a data conversion unit configured to convert input data based on the final random code and output conversion data.
    Type: Application
    Filed: July 29, 2011
    Publication date: July 19, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang Sik KIM, Jun Rye Rho, Sang Chul Lee