Patents by Inventor Jun Rye Rho
Jun Rye Rho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004565Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.Type: ApplicationFiled: September 20, 2023Publication date: January 4, 2024Inventors: Seung Gu JI, Jun Rye RHO
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Patent number: 11797202Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.Type: GrantFiled: July 1, 2020Date of Patent: October 24, 2023Assignee: SK hynix Inc.Inventors: Seung Gu Ji, Jun Rye Rho
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Patent number: 11645008Abstract: An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which target page addresses are omitted; and sequentially outputting, by the memory device, the data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.Type: GrantFiled: January 14, 2021Date of Patent: May 9, 2023Assignee: SK hynix Inc.Inventor: Jun Rye Rho
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Publication number: 20210382656Abstract: An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which the target page addresses are omitted; and sequentially outputting, by the memory device, data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.Type: ApplicationFiled: January 14, 2021Publication date: December 9, 2021Inventor: Jun Rye RHO
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Publication number: 20210191636Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on completion pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.Type: ApplicationFiled: July 1, 2020Publication date: June 24, 2021Inventors: Seung Gu JI, Jun Rye RHO
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Patent number: 9825651Abstract: An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.Type: GrantFiled: December 3, 2015Date of Patent: November 21, 2017Assignee: SK Hynix Inc.Inventors: Jun-Rye Rho, Sung-Gun Cho
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Publication number: 20170017417Abstract: A data storage device includes a nonvolatile memory apparatus including a page including a plurality of chunk areas respectively corresponding to a plurality of data chunks; and a controller including a memory, and suitable for generating parity data by independently encoding one of the plural data chunk, storing the data chunk in one of the plural chunk areas of the page and storing the parity data in the memory as intermediate parity data.Type: ApplicationFiled: December 2, 2015Publication date: January 19, 2017Inventors: Chol Su CHAE, Jun Rye RHO
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Publication number: 20160378595Abstract: An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.Type: ApplicationFiled: December 3, 2015Publication date: December 29, 2016Inventors: Jun-Rye RHO, Sung-Gun CHO
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Patent number: 9513991Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.Type: GrantFiled: March 16, 2013Date of Patent: December 6, 2016Assignee: SK Hynix Inc.Inventor: Jun Rye Rho
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Patent number: 9378134Abstract: Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device. A non-volatile memory system may include a memory controller suitable for controlling a memory; and the memory suitable for performing read and program operations in response to commands from the memory controller, and wherein the memory controller and the memory operate in a high interface mode, and operate in a low interface mode when an operation to read internal data or an operation to receive (N+1)th data is performed during an operation to program Nth data in the memory.Type: GrantFiled: December 11, 2013Date of Patent: June 28, 2016Assignee: SK Hynix Inc.Inventors: Byoung-Sung Yoo, Eui-Jin Kim, Jun-Rye Rho
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Patent number: 9367388Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.Type: GrantFiled: May 13, 2014Date of Patent: June 14, 2016Assignee: SK Hynix Inc.Inventor: Jun Rye Rho
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Patent number: 9171611Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.Type: GrantFiled: June 20, 2014Date of Patent: October 27, 2015Assignee: SK HYNIX INC.Inventor: Jun Rye Rho
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Publication number: 20150235697Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.Type: ApplicationFiled: June 20, 2014Publication date: August 20, 2015Inventor: Jun Rye RHO
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Publication number: 20150154067Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.Type: ApplicationFiled: May 13, 2014Publication date: June 4, 2015Applicant: SK hynix Inc.Inventor: Jun Rye RHO
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Patent number: 8953375Abstract: A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.Type: GrantFiled: August 22, 2012Date of Patent: February 10, 2015Assignee: SK Hynix Inc.Inventors: Jun-Rye Rho, Seok-Hwan Choi
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Publication number: 20140359204Abstract: Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device. A non-volatile memory system may include a memory controller suitable for controlling a memory; and the memory suitable for performing read and program operations in response to commands from the memory controller, and wherein the memory controller and the memory operate in a high interface mode, and operate in a low interface mode when an operation to read internal data or an operation to receive (N+1)th data is performed during an operation to program Nth data in the memory.Type: ApplicationFiled: December 11, 2013Publication date: December 4, 2014Applicant: SK hynix Inc.Inventors: Byoung-Sung YOO, Eui-Jin KIM, Jun-Rye RHO
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Publication number: 20140208187Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.Type: ApplicationFiled: March 16, 2013Publication date: July 24, 2014Applicant: SK HYNIX INC.Inventor: Jun Rye RHO
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Patent number: 8713407Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.Type: GrantFiled: December 24, 2009Date of Patent: April 29, 2014Assignee: Hynix Semiconductor Inc.Inventor: Jun Rye Rho
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Patent number: 8593864Abstract: A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit line in response to a voltage level corresponding to a value of program data.Type: GrantFiled: April 22, 2010Date of Patent: November 26, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jun Rye Rho
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Publication number: 20130170295Abstract: A semiconductor memory device includes an information generation unit configured to convert positions of threshold voltages of memory cells in threshold voltage distributions based on determination voltages included in an overlapping portion between the threshold voltage distributions to generate a plurality of position information codes, and an error correction unit configured to sequentially receive the plurality of position information codes and perform an error correction operation for data of the memory cells.Type: ApplicationFiled: August 22, 2012Publication date: July 4, 2013Inventors: Jun-Rye RHO, Seok-Hwan CHOI