Abstract: A hub device is provided. The hub device includes a first memory, a second memory, and a hub controller. The first memory is configured to store queue setting information for setting a plurality of software queues corresponding to a plurality of processors, and to store doorbell information generated based on the queue setting information and indicating statuses of the plurality of software queues. The second memory is configured to store tag information triggering operations of the plurality of processors. The hub controller is configured to select a target processor from the plurality of processors upon request of a host, select a target queue from at least one software queue corresponding to the target processor, and support communication between the host and the target processor using the target queue.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: Provided herein may be a memory controller. The memory controller may include a shared memory configured to store data, a hardware group configured to generate entry data including result data of an operation corresponding to a command, and output an interrupt signal generated in response to storage of the entry data, and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address for the entry data based on the first index information, and a data transmitter configured to receive, based on a first address, the entry data through a first interface using a data input/output scheme to be set by firmware, and transfer the received entry data to a processor through a second interface using a fixed data input/output scheme.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: Provided herein may be a memory controller. The memory controller may include a shared memory configured to store data, a hardware group configured to generate entry data including result data of an operation corresponding to a command, and output an interrupt signal generated in response to storage of the entry data, and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address for the entry data based on the first index information, and a data transmitter configured to receive, based on a first address, the entry data through a first interface using a data input/output scheme, and transfer the received entry data to a processor through a second interface using a fixed data input/output scheme.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which target page addresses are omitted; and sequentially outputting, by the memory device, the data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.

Abstract: An operating method of a memory system that includes a memory device including a plurality of planes and a plurality of page buffers for the plurality of planes, respectively, and a controller suitable for controlling the memory device, the operating method includes: providing, by the controller, the memory device with page read commands for respective target planes among the plurality of planes; simultaneously reading, by the memory device, data from the target planes and buffering the data in target page buffers corresponding to the respective target planes in response to the page read commands; selectively providing, by the controller, the memory device with an all-plane data output command or respective-plane data output commands from which the target page addresses are omitted; and sequentially outputting, by the memory device, data buffered in the target page buffers, in response to the all-plane data output command or the respective-plane data output commands.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on completion pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages included in the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: A data storage device includes a nonvolatile memory apparatus including a page including a plurality of chunk areas respectively corresponding to a plurality of data chunks; and a controller including a memory, and suitable for generating parity data by independently encoding one of the plural data chunk, storing the data chunk in one of the plural chunk areas of the page and storing the parity data in the memory as intermediate parity data.

Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.

Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.

Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.

Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.

Abstract: Provided is a memory system including a semiconductor memory device including a buffer memory block suitable for storing page data, and including a main memory block, and a controller suitable for generating a combination seed by performing a logical operation on a randomizing seed, a derandomizing seed, and error information, and for providing the generated combination seed to the semiconductor memory device.

Abstract: A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.

Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.

Abstract: A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit line in response to a voltage level corresponding to a value of program data.

Abstract: A semiconductor system includes a host configured to output a command, a control signal, an address signal, and data; and a nonvolatile memory apparatus configured to receive at least one of the command, the control signal, the address signal, and the data from the host, to provide a process result to the host, and to determine data levels of memory cells included in an overlap section of memory cell threshold voltage distributions based on an initial read bias voltage.