Patents by Inventor Jun S. Ko

Jun S. Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5428298
    Abstract: A tester applicable to semiconduction chips having a plurality of pins. The tester comprises a TAB tape having an adhesive surface and a plurality of connecting wires attached to the adhesive surface of the TAB tape and connected to a test card. At a probe region of the tester, probe tips are disposed which come into contact with pads of the semiconductor chip to be tested, upon testing. Each probe tip is made of a palladium layer having a serrated edge grown to shape over a nickel film on a portion of each connecting wire, which portion is disposed at the probe region. The tester can test a semiconductor chip having a plurality of pins and carry out simultaneous probings of a semiconductor chip having the number of pins enabling a TAB chip bonding. Both a functional test and a burn-in test may be carried out with a single test system. Since the tester has many sharp probe tips made of dendritic-grown palladium, it can provide an improvement in proving effect.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: June 27, 1995
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Jun S. Ko
  • Patent number: 5321204
    Abstract: A CCD package and a method for assembling a CCD package utilizing a TAB process. The method comprises the steps of preparing a tape for TAB which has outer leads, inner leads and die bonding paddles, bonding a chip on the paddles and then bonding the free ends of the inner leads on the bonding pads of the chip, connecting the inner leads and the outer leads through insulations, adding a light shield layer beneath the chip, and attaching a glass lid to the surface portions of the inner leads positioned just above the chip. Accordingly, packages of light, laminated and simple structure can be obtained, thereby advantageously enabling the compactness of products utilizing CCD elements. Also, the process is also simplified, thereby decreasing the cost of producing CCD elements.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: June 14, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Jun S. Ko
  • Patent number: 5200367
    Abstract: A method for assembling multilayer packages of semi-conductor elements comprising double molding of the multilayer structure. The method comprises the steps of primarily molding inner leads of a lead frame, secondarily molding the inner leads to form a desired package, and performing in turn die bonding, wire bonding, trimming and forming processes. The double molding process is performed by using an inexpensive molding compound, thereby obtaining packages having a structure equivalent to that of expensive ceramic packages. Accordingly, the manufacture cost of packages is inexpensive and the assembling process is simplified.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: April 6, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Jun S. Ko