Patents by Inventor Jun SAGIYA

Jun SAGIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250266389
    Abstract: An apparatus includes first and second chip bonders. The first chip bonder includes a first holder, a first shaft, a first driver driving the first shaft, and a first pressure sensor detecting a first pressure at which the first driver presses a chip against a bonding target. The second chip bonder includes a second holder, a second shaft, a second driver driving the second shaft, and a second pressure sensor detecting a second pressure at which the second driver presses the chip against the bonding target. A storage stores a first set value of the first pressure and a second set value of the second pressure. A controller controls the first chip bonder to set the first pressure to be the first set value and controls the second chip bonder to set the second pressure to be the second set value.
    Type: Application
    Filed: August 30, 2024
    Publication date: August 21, 2025
    Applicant: Kioxia Corporation
    Inventor: Jun SAGIYA
  • Patent number: 10115704
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Jun Sagiya
  • Publication number: 20160293582
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.
    Type: Application
    Filed: March 4, 2016
    Publication date: October 6, 2016
    Inventor: Jun SAGIYA