Patents by Inventor Jun Seop Chung
Jun Seop Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10509590Abstract: Provided are a memory control device and a method. The memory control device may include a memory device, and a controller operatively coupled to the memory device. The controller may include a receiving unit configured to receive a plurality of commands from a host, and a command processing unit configured to process the commands and order the host to transmit next commands when processing of the commands reaches a trigger point.Type: GrantFiled: July 10, 2017Date of Patent: December 17, 2019Assignee: SK hynix Inc.Inventors: An-Ho Choi, Jun-Seop Chung
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Patent number: 10452431Abstract: A memory system may include: a memory device; and a controller, wherein the controller includes: a receiving unit suitable for receiving a plurality of tasks from a host; and a task processing unit suitable for re-arranging the plurality of the tasks based on the number of the plurality of the tasks and a priority order, and performing the re-arranged tasks.Type: GrantFiled: February 28, 2017Date of Patent: October 22, 2019Assignee: SK hynix Inc.Inventors: An-Ho Choi, Jun-Seop Chung
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Publication number: 20180173462Abstract: Provided are a memory control device and a method. The memory control device may include a memory device, and a controller operatively coupled to the memory device. The controller may include a receiving unit configured to receive a plurality of commands from a host, and a command processing unit configured to process the commands and order the host to transmit next commands when processing of the commands reaches a trigger point.Type: ApplicationFiled: July 10, 2017Publication date: June 21, 2018Inventors: An-Ho CHOI, Jun-Seop CHUNG
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Publication number: 20180157415Abstract: A memory control apparatus may include a memory device including at least two memories respectively coupled to at least two channels, and a controller functionally coupled with the memory device. The controller may receive at least one command for performing a host task from a host, control the memory device to perform the host task with the memories based on the received command, and control the r Memory device such that, when a trigger point of a device task for a memory of the memory device is recognized, a first memory of the memory device coupled with a corresponding channel performs the device task and a second memory of the memory device coupled with the other channel process the host task.Type: ApplicationFiled: July 6, 2017Publication date: June 7, 2018Inventors: An-Ho CHOI, Jun-Seop CHUNG
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Publication number: 20180052710Abstract: A memory system may include: a memory device; and a controller, wherein the controller includes: a receiving unit suitable for receiving a plurality of tasks from a host; and a task processing unit suitable for re-arranging the plurality of the tasks based on the number of the plurality of the tasks and a priority order, and performing the re-arranged tasks.Type: ApplicationFiled: February 28, 2017Publication date: February 22, 2018Inventors: An-Ho CHOI, Jun-Seop CHUNG
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Patent number: 9898199Abstract: A data storage device includes a nonvolatile memory device including a buffer region and a main region; and a controller suitable for controlling a buffer write operation of the nonvolatile memory device such that write-requested first data is stored in the buffer region, and controlling a main write operation of the nonvolatile memory device such that the first data stored in the buffer region is stored in the main region according to a write mode, wherein the nonvolatile memory device performs the buffer write operation regardless of the write mode.Type: GrantFiled: December 29, 2015Date of Patent: February 20, 2018Assignee: Sk Hynix Inc.Inventors: An Ho Choi, Jun Seop Chung
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Publication number: 20170038969Abstract: A data storage device includes a nonvolatile memory device including a buffer region and a main region; and a controller suitable for controlling a buffer write operation of the nonvolatile memory device such that write-requested first data is stored in the buffer region, and controlling a main write operation of the nonvolatile memory device such that the first data stored in the buffer region is stored in the main region according to a write mode, wherein the nonvolatile memory device performs the buffer write operation regardless of the write mode.Type: ApplicationFiled: December 29, 2015Publication date: February 9, 2017Inventors: An Ho CHOI, Jun Seop CHUNG
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Patent number: 8045393Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.Type: GrantFiled: December 31, 2008Date of Patent: October 25, 2011Assignee: Hynix Semiconductor Inc.Inventors: Byung Ryul Kim, Jun Seop Chung, Duck Ju Kim
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Patent number: 7986552Abstract: A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input for programming. The decoder creates the first data by performing a logical operation on the second data that is read from the memory cells and the set data.Type: GrantFiled: March 10, 2009Date of Patent: July 26, 2011Assignee: Hynix Semiconductor Inc.Inventors: Tao Ho Shin, Joong Seob Yang, Jun Seop Chung, You Sung Kim
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Publication number: 20100306579Abstract: A nonvolatile memory device and its programming method includes a memory block having a number of memory cells, a page buffer unit coupled to the memory block and configured to temporarily store program data, to transmit the program data to the memory block, to perform a program operation for the program data, and to output the stored program in response to the memory block being treated as being a bad block, and a control unit configured to transmit the program data to the memory block, temporarily store the program data outputted from the page buffer unit, and transmit the stored program data to another page buffer unit coupled to another memory block.Type: ApplicationFiled: February 4, 2010Publication date: December 2, 2010Inventors: Kwang Ho Baek, Jun Seop Chung, Se Chun Park
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Patent number: 7826277Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes an encoder configured to set random data in a unit of a word line, and generate second data to be programmed in a memory cell by performing logic operation about the random data and first data inputted for program, and a data converting circuit configured to have a decoder for generating the first data by performing logic operation about the second data read from the memory cell and the random data.Type: GrantFiled: June 13, 2008Date of Patent: November 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Tae Ho Shin, Joong Seob Yang, Jun Seop Chung, You Sung Kim
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Patent number: 7751241Abstract: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N?3, N is an integer) read command.Type: GrantFiled: April 13, 2009Date of Patent: July 6, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jong Hyun Wang, Jun Seop Chung, Seok Jin Joo
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Publication number: 20090225597Abstract: A nonvolatile memory device includes a data conversion unit including an encoder and a decoder. The encoder sets data for each of word lines and creates second data to be programmed into a plurality of memory cells by performing a logical operation on the set data and first data input for programming. The decoder creates the first data by performing a logical operation on the second data that is read from the memory cells and the set data.Type: ApplicationFiled: March 10, 2009Publication date: September 10, 2009Inventors: Tao Ho SHIN, Joong Seob YANG, Jun Seop CHUNG, You Sung KIM
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Publication number: 20090225596Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes an encoder configured to set random data in a unit of a word line, and generate second data to be programmed in a memory cell by performing logic operation about the random data and first data inputted for program, and a data converting circuit configured to have a decoder for generating the first data by performing logic operation about the second data read from the memory cell and the random data.Type: ApplicationFiled: June 13, 2008Publication date: September 10, 2009Applicant: Hynix Semiconductor Inc.Inventors: Tae Ho SHIN, Joong Seob Yang, Jun Seop Chung, You Sung Kim
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Publication number: 20090201727Abstract: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N?3, N is an integer) read command.Type: ApplicationFiled: April 13, 2009Publication date: August 13, 2009Applicant: Hynix Semiconductor Inc.Inventors: Jong Hyun WANG, Jun Seop CHUNG, Seok Jin JOO
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Publication number: 20090180329Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.Type: ApplicationFiled: December 31, 2008Publication date: July 16, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Byung Ryul KIM, Jun Seop Chung, Duck Ju Kim
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Patent number: 7518913Abstract: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N?3, N is an integer) read command.Type: GrantFiled: June 29, 2007Date of Patent: April 14, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jong Hyun Wang, Jun Seop Chung, Seok Jin Joo
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Patent number: 7515472Abstract: A page buffer circuit includes a bit line selection circuit, a main register, a program transmission circuit, a temporary register, and a verification transmission circuit. The verification transmission circuit transmits data stored in the temporary register to the main register through a sensing node in response to a transmission control signal during a program verification operation. A memory cell that has been determined to be programmed in a previous program verification process is verified again in a next program verification process.Type: GrantFiled: June 30, 2006Date of Patent: April 7, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jun Seop Chung
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Patent number: 7502885Abstract: A method of operating a packaged flash memory module includes applying a first program or erase command and a first address associated with the first commend to a first flash memory chip of a plurality of flash memory chips that are arranged within the packaged flash memory module; applying a second program or erase command and a second address associated with the second commend to a second flash memory chip of the plurality of flash memory chips that are arranged within the packaged flash memory module, the second command being applied to the second flash memory chip prior to the completion of the first command by the first flash memory chip; and determining whether or not the first flash memory chip has completed the first command.Type: GrantFiled: December 29, 2005Date of Patent: March 10, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jun Seop Chung, Joong Seob Yang
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Publication number: 20080205136Abstract: A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N?3, N is an integer) read command.Type: ApplicationFiled: June 29, 2007Publication date: August 28, 2008Applicant: Hynix Semiconductor Inc.Inventors: Jong Hyun WANG, Jun Seop Chung, Seok Jin Joo