Patents by Inventor Jun Setogawa
Jun Setogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11450355Abstract: A semiconductor memory with temperature dependence is provided. The semiconductor memory includes a memory array, a temperature sensor circuit and a pump circuit. The temperature sensor circuit is configured to provide a temperature dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit is configured to output a charge-pump output voltage to the memory array according to the temperature dependent signal. The charge-pump output voltage depends on the temperature dependent signal.Type: GrantFiled: May 3, 2021Date of Patent: September 20, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Jun Setogawa
-
Patent number: 10818337Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.Type: GrantFiled: August 2, 2017Date of Patent: October 27, 2020Assignee: ZENTEL JAPAN CORPORATIONInventors: Bunsho Kuramori, Mineo Noguchi, Akihiro Hirota, Masahiro Ishihara, Mitsuru Yoneyama, Takashi Kubo, Masaru Haraguchi, Jun Setogawa, Hironori Iga
-
Publication number: 20190362774Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.Type: ApplicationFiled: August 2, 2017Publication date: November 28, 2019Inventors: Bunsho KURAMORI, Mineo NOGUCHI, Akihiro HIROTA, Masahiro ISHIHARA, Mitsuru YONEYAMA, Takashi KUBO, Masaru HARAGUCHI, Jun SETOGAWA, Hironori IGA
-
Patent number: 9170637Abstract: A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.Type: GrantFiled: April 13, 2015Date of Patent: October 27, 2015Assignee: Renesas Electronics CorporationInventors: Mamoru Sakugawa, Masamichi Fujito, Jun Setogawa, Masaru Takahashi, Shinsuke Yoshimura
-
Publication number: 20150220130Abstract: A data processing device, includes a central processing unit configured to operate in accordance with a program; a register capable of setting a first mode and a second mode; a non-volatile memory; a sequencer configured to control the non-volatile memory; and a first clock circuit for supplying a first clock to the central processing unit and the non-volatile memory, wherein the first mode is a mode in which the central processing unit is operated within a first range of an external supply voltage, wherein the second mode is a mode in which the central processing unit is operated within a second range of the external supply voltage, the second range includes the first range and a relatively low voltage lower than the lower limit voltage of the first range.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Mamoru SAKUGAWA, Masamichi FUJITO, Jun SETOGAWA, Masaru TAKAHASHI, Shinsuke YOSHIMURA
-
Patent number: 9026823Abstract: A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.Type: GrantFiled: August 26, 2010Date of Patent: May 5, 2015Assignee: Renesas Electronics CorporationInventors: Mamoru Sakugawa, Masamichi Fujito, Jun Setogawa, Masaru Takahashi, Shinsuke Yoshimura
-
Publication number: 20130145190Abstract: A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.Type: ApplicationFiled: August 26, 2010Publication date: June 6, 2013Applicant: Renesas Electronics CorporationInventors: Mamoru Sakugawa, Masamichi Fujito, Jun Setogawa, Masaru Takahashi, Shinsuke Yoshimura
-
Patent number: 8441880Abstract: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. An operational stability of the nonvolatile memory is realized.Type: GrantFiled: June 29, 2011Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Toru Matsushita, Ken Matsubara, Takashi Iwase, Hidenori Mitani, Jun Setogawa, Fumiko Yamada
-
Publication number: 20120002498Abstract: Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.Type: ApplicationFiled: June 29, 2011Publication date: January 5, 2012Inventors: Toru Matsushita, Ken Matsubara, Takashi Iwase, Hidenori Mitani, Jun Setogawa, Fumiko Yamada
-
Patent number: 7630239Abstract: The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.Type: GrantFiled: September 11, 2007Date of Patent: December 8, 2009Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Jun Setogawa
-
Publication number: 20080175066Abstract: The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.Type: ApplicationFiled: September 11, 2007Publication date: July 24, 2008Inventors: Minoru Senda, Jun Setogawa
-
Publication number: 20070164415Abstract: A semiconductor memory device has the group of longest signal lines configured in a twisted wiring scheme, the group of signal lines of intermediate length configured in a shield wiring scheme, and the group of shortest signal lines configured in a single wiring scheme. As a whole, degradation in signal waveform and improvement in layout efficiency can both be achieved.Type: ApplicationFiled: January 10, 2007Publication date: July 19, 2007Applicant: Renesas Technology Corp.Inventor: Jun Setogawa
-
Patent number: 7092314Abstract: A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.Type: GrantFiled: July 6, 2005Date of Patent: August 15, 2006Assignee: Renesas Technology Corp.Inventor: Jun Setogawa
-
Publication number: 20050243643Abstract: A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.Type: ApplicationFiled: July 6, 2005Publication date: November 3, 2005Applicant: Renesas Technology Corp.Inventor: Jun Setogawa
-
Patent number: 6775190Abstract: A detection circuit in a semiconductor memory device includes a first latch circuit and a second latch circuit. The first latch circuit latches a data strobe signal at a rise of a clock signal after a write latency passes. The second latch circuit receives an output signal of the first latch circuit at a rise of a clock signal to output a detection signal. Circuits in the semiconductor memory device are controlled by a detection signal. With such an operation applied, the semiconductor memory device grasps a correct phase difference between a data strobe signal and a clock signal, thereby enabling a normal operation.Type: GrantFiled: July 24, 2002Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventor: Jun Setogawa
-
Publication number: 20040081012Abstract: A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.Type: ApplicationFiled: April 8, 2003Publication date: April 29, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Jun Setogawa
-
Patent number: 6711084Abstract: The output of a ring oscillator that receives an internal power supply potential as an operating power supply potential to conduct an oscillation operation is counted by a counter that receives an external power supply potential as an operating power supply potential, and reset is canceled. The circuit that operates with an internal power supply potential can be reliably reset even when the rise of the internal power supply potential is delayed. By adjusting the number of stages of the inverter of a ring oscillator and the number of bits of the counter, the power-on reset time can be adjusted while suppressing increase of the area. An appropriate power-on reset signal can be generated to prevent erroneous operation even in the case where the rise of the internal power supply potential lags behind the rise of the external power supply potential.Type: GrantFiled: July 26, 2002Date of Patent: March 23, 2004Assignee: Renesas Technology Corp.Inventors: Takuya Ishida, Jun Setogawa
-
Patent number: 6606274Abstract: The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.Type: GrantFiled: January 7, 2002Date of Patent: August 12, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Jun Setogawa
-
Publication number: 20030147299Abstract: The semiconductor memory device includes a synchronizing signal generating circuit. The synchronizing signal generating circuit generates the internal clock, a dummy clock and the internal data strobe signal. The dummy clock is generated on the basis of clock by the same circuit configuration as the internal DQS generating circuit. Each of plural serial/parallel conversion circuits latch data sequentially in synchronism with the internal data strobe signal, the dummy clock and the internal clock to output the data to internal circuits. As a result, a switch can be performed between synchronizing signals for operation on data from the internal data strobe signal to the internal clock even if a circuit generating the internal data strobe signal is different from a circuit generating the internal clock.Type: ApplicationFiled: August 5, 2002Publication date: August 7, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Jun Setogawa
-
Publication number: 20030142572Abstract: The output of a ring oscillator that receives an internal power supply potential as an operating power supply potential to conduct an oscillation operation is counted by a counter that receives an external power supply potential as an operating power supply potential, and reset is canceled. The circuit that operates with an internal power supply potential can be reliably reset even when the rise of the internal power supply potential is delayed. By adjusting the number of stages of the inverter of a ring oscillator and the number of bits of the counter, the power-on reset time can be adjusted while suppressing increase of the area. An appropriate power-on reset signal can be generated to prevent erroneous operation even in the case where the rise of the internal power supply potential lags behind the rise of the external power supply potential.Type: ApplicationFiled: July 26, 2002Publication date: July 31, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takuya Ishida, Jun Setogawa