Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: A floating-point number operation method applied to multiplication operation of a first floating-point number and a second floating-point number is provided. The first floating point number includes a first symbol, a first exponent and a first mantissa. The second floating point number includes a second symbol, a second exponent and a second mantissa. The method includes using an arithmetic unit to perform: comparing the first exponent to an exponent threshold, wherein when the first exponent is not less than the exponent threshold, generating a mantissa operation result by multiplying the first mantissa and the second mantissa when the first exponent is not less than the exponent threshold value; and generating a calculated floating point number according to the mantissa operation result and an exponent operation result of the first exponent and the second exponent.

Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: A processor adapted for neural network operation is provided to include a scratchpad memory, a processor core, a neural network accelerator coupled to the processor core, and a arbitration unit coupled to the scratchpad memory, the processor core and the neural network accelerator. The processor core and the neural network accelerator share the scratchpad memory via the arbitration unit.