Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line capping layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line canning layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line capping layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. A plurality of parallel bit line patterns are placed on the bit line interlayer insulating layer. Each of the bit line patterns has a bit line and a bit line capping layer pattern stacked thereon. Bit line spacers covers side walls of the bit line patterns, buried holes penetrate predetermined regions of the bit line interlayer insulating layer between the bit line patterns. And a plurality of storage node contact plugs are placed between the bit line patterns surrounding by the bit line spacers. At this time, the storage node contact plugs fill the buried holes.

Abstract: A method of opening a repair fuse of a semiconductor device in a stable fashion is provided. According to the method, an upper plate electrode and a blocking dielectric layer are formed on a cell region and a fuse region, thereby opening the repair fuse completely.

Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

Abstract: A method of opening a repair fuse of a semiconductor device in a stable fashion is provided. According to the method, an upper plate electrode and a blocking dielectric layer are formed on a cell region and a fuse region, thereby opening the repair fuse completely.

Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.