Abstract: The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the lower end of the substrate and direct leakage of current from the source region/drain region into the lower ends of the channels, but also can facilitate heat release of the substrate by forming trench inner spacers (TIS) and thus preventing source region/drain region impurities from diffusing into the substrate, and a method for manufacturing the same.

Abstract: The present disclosure relates to a cell-derived vesicle rich in intracellular protein homeostasis regulators, and to a method of preparing same. The cell-derived vesicle of the present disclosure is characterized by containing an abundance of a specific protein compared to that in a naturally secreted exosome or the originated cell, and by virtue of said characteristic, can be utilized for various purposes such as in a pharmaceutical composition, a diagnostic composition, and a composition for drug delivery. Using the cell-derived vesicle rich in intracellular protein homeostasis regulators and the method of preparing same of the present disclosure, it is possible to easily deliver the intracellular protein homeostasis regulators to a target, such as a cell, thereby easily maintaining protein homeostasis in cells.

Abstract: Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: Disclosed is a metal source/drain-based field effect transistor having a structure that replaces a portion of a semiconductor of a source/drain with a metal and a method of manufacturing the same. By replacing the source/drain region with the source/drain metal region, increase of the parasitic resistance of a conventional three-dimensional MOSFET of several tens of nanometers, lattice mismatch of the source/drain during selective epitaxial growth, and self-heating effect can be fundamentally solved. Further, since the metal is deposited after the partial etching of the source/drain region or the selective epitaxial growth is partially performed under the conventional CMOS process, the process can be performed without using any additional mask.

Abstract: A method for setting of a semiconductor manufacturing parameter according to an embodiment is a method performed in a computing device including one or more processors, and a memory for storing one or more programs executed by the one or more processors, the method including an operation of inputting manufacturing parameters for manufacturing a semiconductor to a neural network model and an operation of training the neural network model to predict at least one of power and delay of the semiconductor based on the input manufacturing parameters.

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

Abstract: Disclosed in a CASCODE device in which multiple transistors are stacked in a vertical direction and connected in series. The CASCODE device exhibits improvements in device/circuit intrinsic gain (GmRo) that is a performance index for analog/RF applications, cutoff frequency (Ft), and maximum oscillation frequency (Fmax). A method of manufacturing the CASCODE device is also disclosed.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: Disclosed is a field effect transistor including an insulating film disposed between a source/drain region and a substrate. Since the insulating film prevents current leakage under a channel, it is not necessary to form a punch-through stopper. Further disclosed is a method of forming a field effect transistor.

Abstract: Disclosed is a metal source/drain-based field effect transistor having a structure that replaces a portion of a semiconductor of a source/drain with a metal and a method of manufacturing the same. By replacing the source/drain region with the source/drain metal region, increase of the parasitic resistance of a conventional three-dimensional MOSFET of several tens of nanometers, lattice mismatch of the source/drain during selective epitaxial growth, and self-heating effect can be fundamentally solved. Further, since the metal is deposited after the partial etching of the source/drain region or the selective epitaxial growth is partially performed under the conventional CMOS process, the process can be performed without using any additional mask.