Patents by Inventor Jun-Soo Bae
Jun-Soo Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240106085Abstract: A secondary battery includes: an electrode assembly including a first electrode plate from which a first current collecting tab protrudes, a second electrode plate from which a second current collecting tab protrudes, and a separator between the first electrode plate and the second electrode plate; a case accommodating the electrode assembly; and a current collector plate electrically connected to the first current collecting tab and including protrusions, and the first current collecting tab is vertically coupled to the current collector plate and includes coupling grooves to which the protrusions are coupled.Type: ApplicationFiled: August 30, 2023Publication date: March 28, 2024Inventors: Kwang Soo BAE, Jun Sun YONG, Jun Hyung LEE
-
Patent number: 10164173Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: GrantFiled: July 25, 2017Date of Patent: December 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Shi-Jung Kim, Mi-Lim Park, Jun-Soo Bae, Seung-Woo Lee
-
Publication number: 20170324031Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: ApplicationFiled: July 25, 2017Publication date: November 9, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu-Man HWANG, Shi-Jung KIM, Mi-Lim PARK, Jun-Soo BAE, Seung-Woo LEE
-
Patent number: 9761792Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: GrantFiled: October 20, 2015Date of Patent: September 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Shi-Jung Kim, Mi-Lim Park, Jun-Soo Bae, Seung-Woo Lee
-
Publication number: 20160155934Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.Type: ApplicationFiled: October 20, 2015Publication date: June 2, 2016Inventors: Kyu-Man HWANG, Shi-Jung KIM, Mi-Lim PARK, Jun-Soo BAE, Seung-Woo LEE
-
Patent number: 8772121Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: GrantFiled: April 10, 2012Date of Patent: July 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
-
Patent number: 8513051Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.Type: GrantFiled: February 19, 2010Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Ho Ha, Bong-Jin Kuh, Ji-Hye Yi, Jun-Soo Bae
-
Publication number: 20120273741Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.Type: ApplicationFiled: April 10, 2012Publication date: November 1, 2012Inventors: Kyu-Man HWANG, Jun-Soo BAE, Sung-Un KWON, Kwang-Ho PARK
-
Patent number: 8238147Abstract: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.Type: GrantFiled: September 11, 2008Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Bae, Hideki Horii, Jong-Chan Shin
-
Patent number: 8237141Abstract: A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by InXSbYTeZ or, alternatively, with substitutions of silicon and/or tin for indium, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer.Type: GrantFiled: January 19, 2010Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myung-jin Kang, Jun-soo Bae, Doo-hwan Park, Eun-hee Cho
-
Patent number: 8168535Abstract: A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.Type: GrantFiled: April 12, 2011Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Bae, Suk-Hun Choi, Won-Jun Lee, Joon-Sang Park
-
Patent number: 8143653Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.Type: GrantFiled: November 16, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Jong-Soo Seo, Young-Kug Moon, Jun-Soo Bae, Kwang-Jin Lee
-
Patent number: 8139432Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.Type: GrantFiled: October 8, 2010Date of Patent: March 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-gil Choi, Beak-hyung Cho, Jun-Soo Bae, Kwang-Jin Lee
-
Patent number: 8134866Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.Type: GrantFiled: January 6, 2010Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Bae, Kwang-Jin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Hye-Jin Kim
-
Patent number: 8116117Abstract: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.Type: GrantFiled: December 7, 2009Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yeong Cho, Ki-Sung Kim, Du-Eung Kim, Kwang-Jin Lee, Jun-Soo Bae
-
Publication number: 20110306173Abstract: A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.Type: ApplicationFiled: April 12, 2011Publication date: December 15, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Soo BAE, Suk-Hun CHOI, Won-Jun LEE, Joon-Sang PARK
-
Patent number: 8050084Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.Type: GrantFiled: September 29, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Bae, Kwang-Jin Lee, Beak-Hyung Cho
-
Patent number: 8035145Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.Type: GrantFiled: May 4, 2010Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Bae, Jang-Eun Lee, Hyun-Jo Kim, Se-Chung Oh, Kyung-Tae Nam
-
Patent number: 7943918Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.Type: GrantFiled: September 28, 2009Date of Patent: May 17, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Hee Park, Ju-Chul Park, Jun-Soo Bae, Bong-Jin Kuh, Yong-Ho Ha
-
Publication number: 20110080775Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.Type: ApplicationFiled: September 29, 2010Publication date: April 7, 2011Inventors: Jun-Soo Bae, Kwang-Jin Lee, Beak-Hyung Cho