Abstract: There is provided a solid-state imaging device having a configuration suitable for high integration. The solid-state imaging device includes a semiconductor layer, a photoelectric converter, a storage capacitor, and a first transistor. The photoelectric converter is provided in the semiconductor layer, and generates an electric charge corresponding to a received light amount by photoelectric conversion. The storage capacitor is provided on the semiconductor layer, and includes a first insulating film having a first electrical film thickness. The first transistor is provided on the semiconductor layer, and includes a second insulating film having a second electrical film thickness larger than the first electrical film thickness.

Abstract: There is provided a solid-state imaging device having a configuration suitable for high integration. The solid-state imaging device includes a semiconductor layer, a photoelectric converter, a storage capacitor, and a first transistor. The photoelectric converter is provided in the semiconductor layer, and generates an electric charge corresponding to a received light amount by photoelectric conversion. The storage capacitor is provided on the semiconductor layer, and includes a first insulating film having a first electrical film thickness. The first transistor is provided on the semiconductor layer, and includes a second insulating film having a second electrical film thickness larger than the first electrical film thickness.

Abstract: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer.

Abstract: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer.

Abstract: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer.

Abstract: A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer.

Abstract: A relatively high-resistance first compound film of a semiconductor and a metal is formed on a surface of a semiconductor region in self alignment by a relatively low-temperature first annealing. The relatively high-resistance first compound film is converted into a relatively low-resistance second compound film by a relatively high-temperature second annealing which is done after an insulating film is formed above the first compound film. Hence, the annealing aiming at decreasing a resistance of the compound film can serve as another annealing as well. The number of times of annealing applied to the compound film the resistance of which has been decreased is small, and a thinning effect of the compound film can be suppressed.

Abstract: An N-type impurity is ion-implanted in the exposed surface of a semiconductor substrate, thereby forming N-type diffusion layers. A P-type impurity is ion-implanted in the semiconductor substrate covered with a cover film, thereby forming P-type diffusion layers. A compound film of a semiconductor and a metal is formed on each of the surfaces of the N-type and P-type diffusion layers.

Abstract: A process of fabricating a semiconductor device, includes the steps of: forming a side wall insulating film on a side portion of a gate electrode formed on a silicon substrate; forming a source/drain region in the silicon substrate, and subjecting the source/drain region to an activating heat treatment; forming a metal film on the surface of the source/drain region, and making the metal film react with the silicon substrate by a heat treatment thereby forming a silicide layer; wherein a first furnace heat treatment is performed after formation of the side wall insulating film and before formation the source/drain region; and an oxide film formed on the surface of the silicon substrate is removed before formation of the metal film, a surface side of the silicon substrate is made amorphous by doping ions of arsenic into the silicon substrate, and the metal film is formed.