Patents by Inventor Jun Sugiura
Jun Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8728770Abstract: A method for the enzymatic saccharification of a lignocellulosic raw material, including adding a pretreated lignocellulosic raw material as a material suitable for an enzymatic saccharification reaction, together with an electrolyte containing a water-soluble salt, to water that contains a celluolose saccharification enzyme; saccharifying the raw material by an enzymatic saccharification reaction, as a suspension of the raw material having an electrical conductivity adjusted to 5-25 mS/cm; separating and recovering a reaction product and an enzyme-containing solution from the enzymatically saccharified treatment suspension; and recycling the recovered enzyme-containing solution as the enzyme for the enzymatic saccharification step.Type: GrantFiled: August 31, 2011Date of Patent: May 20, 2014Assignee: Oji Holdings CorporationInventors: Kotaro Ishikawa, Atsushi Furujyo, Yaping Chao, Hisako Tokuno, Jun Sugiura, Motohiro Matsumura
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Publication number: 20130157318Abstract: A method for the enzymatic saccharification of a lignocellulosic raw material, including adding a pretreated lignocellulosic raw material as a material suitable for an enzymatic saccharification reaction, together with an electrolyte containing a water-soluble salt, to water that contains a celluolose saccharification enzyme; saccharifying the raw material by an enzymatic saccharification reaction, as a suspension of the raw material having an electrical conductivity adjusted to 5-25 mS/cm; separating and recovering a reaction product and an enzyme-containing solution from the enzymatically saccharified treatment suspension; and recycling the recovered enzyme-containing solution as the enzyme for the enzymatic saccharification step.Type: ApplicationFiled: August 31, 2011Publication date: June 20, 2013Applicant: Oji Holdings CorporationInventors: Kotaro Ishikawa, Atsushi Furujyo, Yaping Chao, Hisako Tokuno, Jun Sugiura, Motohiro Matsumura
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Publication number: 20110207177Abstract: The present invention provides a pretreatment method which enables the promotion of the enzymatic glycosylation of lignocellulose under relatively mild conditions by using a tree bark as a raw material with less energy. Specifically the present invention provides a step for producing a sugar from a tree bark, which is characterized by having the following steps: an alkali treatment step of immersing the tree bark in an alkali compound solution; a refining treatment step of refining the alkali treated tree bark mechanically into fine pieces; and an enzymatic glycosylation step of glycosylating the refined tree bark with an enzyme. The present invention also provides a method of producing an ethanol.Type: ApplicationFiled: October 29, 2009Publication date: August 25, 2011Applicant: OJI PAPER CO., LTD.Inventors: Jun Sugiura, Atsushi Furujyo, Yaping Chao, Yuko Igarashi, Yuji Iwasaki, Masayuki Ichinomiya, Makoto Sakaino
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Patent number: 6942754Abstract: Xylooligosaccharide is produced from a lignocellulose pulp by enzyme-treating a lignocellulose pulp with hemicellulase, filtering the resultant reaction mixture to separate a liquid fraction from the enzyme-treated pulp, subjecting the separated liquid fraction to a permeation treatment through a separation membrane to separate a non-permeated fraction containing xylooligosaccharide-lignin complex with an increased concentration from a permeated fraction, collecting the non-permeated fraction, and separating and recovering xylooligosaccharide from the collected non-permeated fraction.Type: GrantFiled: April 22, 2002Date of Patent: September 13, 2005Assignee: Oji Paper Co., Ltd.Inventors: Yoshiya Izumi, Jun Sugiura, Hitoshi Kagawa, Naoya Azumi
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Publication number: 20050181485Abstract: A method for treating woodchips, comprising the steps of: preparing a DNA encoding an antisense RNA substantially complementary to the whole or a part of a transcription product of a cellulolytic enzyme gene derived from Basidiomycete; preparing a vector comprising (a) the above DNA, or (b) a recombinant DNA comprising the above DNA and a DNA fragment having a promoter activity, wherein the above DNA binds to the above DNA fragment such that an antisense RNA of the cellulolytic enzyme gene is generated as a result of transcription; transforming host cells with the above vector, so as to prepare the host cells having a suppressed cellulolytic enzyme activity; and inoculating the above host cells having a suppressed cellulolytic enzyme activity into woodchips to treat them.Type: ApplicationFiled: February 25, 2003Publication date: August 18, 2005Inventors: Akira Tsukamoto, Seiji Nakagame, Mari Kabuto, Jun Sugiura, Hisako Sakaguchi, Atsushi Furujyo
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Patent number: 6894334Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: March 3, 2003Date of Patent: May 17, 2005Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6824646Abstract: Lignocellulose pulp is bleached by bleaching a pulp in aqueous alkali solution with oxygen and treating the pulp with a hemicellulase, while a liquid fraction delivered from the enzyme treatment step is separated from the hemicellulase treated reaction mixture, and subjected to a penetration treatment through a separation membrane, for example, reverse osmosis membrane, to separate a permeated fraction from a non-permeated fraction; the permeated fraction is fed to the alkali-oxygen bleaching (oxygen delignification) step and is used as a liquid medium of the bleaching system.Type: GrantFiled: April 22, 2002Date of Patent: November 30, 2004Assignee: OJI Paper Co., Ltd.Inventors: Yoshiya Izumi, Jun Sugiura, Hitoshi Kagawa, Naoya Azumi
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Publication number: 20040155289Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.Type: ApplicationFiled: February 10, 2004Publication date: August 12, 2004Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 6737318Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.Type: GrantFiled: December 3, 2001Date of Patent: May 18, 2004Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Publication number: 20030189255Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: ApplicationFiled: March 3, 2003Publication date: October 9, 2003Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6548847Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: July 9, 2001Date of Patent: April 15, 2003Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Publication number: 20020195213Abstract: Xylooligosaccharide is produced from a lignocellulose pulp by enzyme-treating a lignocellulose pulp with hemicellulase, filtering the resultant reaction mixture to separate a liquid fraction from the enzyme-treated pulp, subjecting the separated liquid fraction to a permeation treatment through a separation membrane to separate a non-permeated fraction containing xylooligosaccharide-lignin complex with an increased concentration from a permeated fraction, collecting the non-permeated fraction, and separating and recovering xylooligosaccharide from the collected non-permeated fraction.Type: ApplicationFiled: April 22, 2002Publication date: December 26, 2002Inventors: Yoshiya Izumi, Jun Sugiura, Hitoshi Kagawa, Naoya Azumi
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Publication number: 20020174962Abstract: Lignocellulose pulp is bleached by bleaching a pulp in aqueous alkali solution with oxygen and treating the pulp with a hemicellulase, while a liquid fraction delivered from the enzyme treatment step is separated from the hemicellulase treated reaction mixture, and subjected to a penetration treatment through a separation membrane, for example, reverse osmosis membrane, to separate a permeated fraction from a non-permeated fraction; the permeated fraction is fed to the alkali-oxygen bleaching (oxygen delignification) step and is used as a liquid medium of the bleaching system.Type: ApplicationFiled: April 22, 2002Publication date: November 28, 2002Inventors: Yoshiya Izumi, Jun Sugiura, Hitoshi Kagawa, Naoya Azumi
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Publication number: 20020127793Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: ApplicationFiled: December 3, 2001Publication date: September 12, 2002Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Publication number: 20020028574Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected,, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: ApplicationFiled: July 27, 2001Publication date: March 7, 2002Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Publication number: 20020017669Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: ApplicationFiled: July 9, 2001Publication date: February 14, 2002Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6342412Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: December 14, 1999Date of Patent: January 29, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6281071Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.Type: GrantFiled: May 25, 1999Date of Patent: August 28, 2001Assignee: Hiatchi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Isamu Asano, Mitsuaki Horiuchi, Jun Sugiura, Hiroko Kaneko, Shinji Shimizu, Atsushi Hiraiwa, Hidetsugu Ogishi, Masakazu Sagawa, Masami Ozawa, Toshihiro Sekiguchi
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Patent number: 6169324Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: October 6, 1999Date of Patent: January 2, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6127255Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.Type: GrantFiled: October 3, 1997Date of Patent: October 3, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane