Patents by Inventor Jun Sumino

Jun Sumino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11683942
    Abstract: A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: June 20, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Jun Sumino, Masayuki Tazaki, Hideyuki Fukata
  • Patent number: 11295812
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 10783961
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 10622067
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20200091241
    Abstract: A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.
    Type: Application
    Filed: May 1, 2018
    Publication date: March 19, 2020
    Inventors: JUN SUMINO, MASAYUKI TAZAKI, HIDEYUKI FUKATA
  • Publication number: 20190318782
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20190311767
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 10438661
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 10395731
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20190080759
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 10074425
    Abstract: Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Sumino, Makoto Kitagawa
  • Patent number: 10050085
    Abstract: Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 14, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Sumino
  • Publication number: 20180144792
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 24, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 9935266
    Abstract: Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 3, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Sumino
  • Patent number: 9911489
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20170294229
    Abstract: Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 12, 2017
    Inventors: Jun Sumino, Makoto Kitagawa
  • Publication number: 20170288141
    Abstract: Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventor: Jun Sumino
  • Publication number: 20170256590
    Abstract: Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventor: Jun Sumino
  • Patent number: 9728722
    Abstract: Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Sony Corporation
    Inventor: Jun Sumino
  • Patent number: RE46636
    Abstract: A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: December 12, 2017
    Assignee: SONY CORPORATION
    Inventors: Jun Sumino, Motonari Honda